From patchwork Thu Feb 27 15:52:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 869172 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 214E326E63C; Thu, 27 Feb 2025 15:53:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740671593; cv=none; b=aXrqgwCRiONextu2kgDkwiQTQpZ51Pm5MFc0C2idtZmGlaApuEVCTaOaG+pFi6Vu+5OOukN+tJyaDVmwS2nsdWzleB8Mst26u+62iKWhmv/nTbUXI9vuLhNe4WcV1V7iZRByL6rbhhZNDub4l2153MTZieYFz/MZyoWROwKhgew= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740671593; c=relaxed/simple; bh=8iqa25WLbQ368CsVaPvdLG58CjAYmr/BYZ/mJasbeKA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Gmwo5Q9XS56OKMHTwQ+4nJQF64dggYqd+XNA2Pvjgo2S5WxUsr9uyrDBlbNgMZoK+Nxue/PBs924en6OpY658bTFF1t6a6F1OH1L2tPufunS2ezgw2XHqbQEw7k8rA9LKv3zyZMTqLwAyS2QI25RpUf5akeu8nYzV9R2tTbOfjU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=pOfGQdDw; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="pOfGQdDw" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1740671591; x=1772207591; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8iqa25WLbQ368CsVaPvdLG58CjAYmr/BYZ/mJasbeKA=; b=pOfGQdDwjrcRLS5KkSlmxTcbJ/sEZNHdOA1WZT6mKLzHyToT01E6KZ/r 7lzrAysYYX/42QxhO86pIWSW2TdGTrpqsCAO7X+6b3aaQDg7v6aFhc62L b/8n3Xo47v0tRJFfgulj4zWBXO882iB2orNN4+TDKXYGA2D66jrSX0DoC tIyBf6fBeHYt9GpQcS7i8pXi76ob0jfTnBXfFUtAX4DNB1SrYFdX1wzhX S28dQ8IgRFXuOEiA+xqzOUO1J8qmEpjvA9rMMRJLh4ek7lVA/Kxtp5Dmx czIFq4xPlK3a3ORAwcoivhMAHHLHhfukkRaFj0tQJZfrmcck8OcOTH5FC w==; X-CSE-ConnectionGUID: xBkIAngZQVSwQhIMCQbtUA== X-CSE-MsgGUID: M217Fjv2TPm3bM4HNcQrFg== X-IronPort-AV: E=Sophos;i="6.13,320,1732604400"; d="scan'208";a="38638182" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 27 Feb 2025 08:52:59 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 27 Feb 2025 08:52:46 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 27 Feb 2025 08:52:46 -0700 From: To: , , , , , , , , CC: , , , , , , "Ryan Wanner" Subject: [PATCH v3 17/21] ARM: dts: microchip: sama7d65: Add RTT and GPBR Support for sama7d65 SoC Date: Thu, 27 Feb 2025 08:52:04 -0700 Message-ID: <6a1c058edee3fe1459dcb3a93a0a789a9ffff5f3.1740671156.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add RTT support for SAMA7D65 SoC. The GPBR is added so the SoC is able to store the RTT time data. Signed-off-by: Ryan Wanner --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index b0a676623100..aadeea132289 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -120,6 +120,13 @@ shdwc: poweroff@e001d200 { status = "disabled"; }; + rtt: rtc@e001d300 { + compatible = "microchip,sama7d65-rtt", "atmel,at91sam9260-rtt"; + reg = <0xe001d300 0x30>; + interrupts = ; + clocks = <&clk32k 0>; + }; + clk32k: clock-controller@e001d500 { compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc"; reg = <0xe001d500 0x4>; @@ -132,6 +139,11 @@ chipid@e0020000 { reg = <0xe0020000 0x8>; }; + gpbr: gpbr@e001d700 { + compatible = "microchip,sama7d65-gpbr", "syscon"; + reg = <0xe001d700 0x48>; + }; + dma2: dma-controller@e1200000 { compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; reg = <0xe1200000 0x1000>;