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SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230016)(4636009)(346002)(136003)(376002)(396003)(39860400002)(46966006)(36840700001)(40470700004)(110136005)(54906003)(6636002)(86362001)(336012)(316002)(16526019)(83380400001)(40480700001)(2616005)(47076005)(186003)(41300700001)(478600001)(6666004)(82310400005)(426003)(36860700001)(26005)(356005)(7696005)(8936002)(82740400003)(2906002)(40460700003)(36756003)(70586007)(81166007)(8676002)(70206006)(5660300002)(4326008)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2022 10:05:02.4077 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 86b3f28f-345f-412a-dc8e-08da66497bf5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT007.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3616 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org This cppc_req_cached valued should be prefetched during amd_pstate_cpu_init call period, then the amd_pstate_update() will get correct cached value before updating the perf to change the cpu perf level.The cached values are read through MSR interface, so here use shared_mem flag to check the registers are accessible Also the core performance boost state will be initialized through hardware configuration register * shared_mem flag is used for the shared memory type CPPC implementation which dose not support MSR interface operation Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 43e6df9f67f6..d8c4153dbe4f 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -92,6 +92,8 @@ struct amd_aperf_mperf { * @prev: Last Aperf/Mperf/tsc count value read from register * @freq: current cpu frequency value * @boost_supported: check whether the Processor or SBIOS supports boost mode + * @precision_boost_off: the core performance boost disabled state + * @cppc_hw_conf_cached: the cached hardware configuration register * * The amd_cpudata is key private data for each CPU thread in AMD P-State, and * represents all the attributes and goals that AMD P-State requests at runtime. @@ -117,6 +119,7 @@ struct amd_cpudata { u64 freq; bool boost_supported; + bool precision_boost_off; u64 cppc_hw_conf_cached; }; @@ -547,12 +550,17 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) cpudata->lowest_nonlinear_freq = lowest_nonlinear_freq; policy->driver_data = cpudata; + if (!shared_mem) { + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_HW_CTL, &value); + if (ret) + return ret; + cpudata->precision_boost_off = value & AMD_CPPC_PRECISION_BOOST_ENABLED; - ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_HW_CTL, &value); - if (ret) - return ret; - WRITE_ONCE(cpudata->cppc_hw_conf_cached, value); - + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value); + if (ret) + return ret; + WRITE_ONCE(cpudata->cppc_req_cached, value); + } amd_pstate_boost_init(cpudata); return 0;