From patchwork Wed Apr 23 01:46:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 884182 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D096C264A72; Wed, 23 Apr 2025 01:47:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745372823; cv=none; b=gBzi2hOSsKHr6K1ZQZrPl+EKVkXVvJ9nGP063f4Z0Q5TdNRCkcpWtGCA0EI6Sv8xsBRDVKuJTNV8vsMZ4XKorlnAQ3loHkN99oQiMhhlR4N65AF/x5JTAYgxbz/A3TfH0KwKZq2CfRLEEYxJBjnMPXK3McpXYRs97DGZmgagqoA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745372823; c=relaxed/simple; bh=UcQq1FFSIkxtUl0R2B0U9yrBSqRLeyIDteqW0GNuh/I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ihgn63tLI92mEmxCgcBF/zu6Kzm7qRFu8MgQg4BL0P7cQ18BF/uRHa4012DvKPN6ql1+pvtMP0oIUb46/NnecnfZ38rJSQJDcwMGdM18a4ngdVqPteR/lRvMQaR66avaSxdINkn45t+XJOMHvrPogz9BdJsP+UwqEzuLtrEgT1E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eMAzY9Pp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eMAzY9Pp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9B990C4CEED; Wed, 23 Apr 2025 01:47:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745372823; bh=UcQq1FFSIkxtUl0R2B0U9yrBSqRLeyIDteqW0GNuh/I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eMAzY9Ppey6y7/HLO4nPRmuCxvZhpD465dwB08aAXptGaY90P/3mPUKK8+zUGMYDK gIhVc3/vzfJxBUSeWzaQ6GzH9RC69vJXzO4eJ7iaC3J5WdTPlZ99TbWLoBUh/EoGMX hq5X5v6g8qCAhBiq4P+FRTnvy06WdVI7hNrbo9rRyssbNHBNFmW286gRjH/zsCGcbx 8yLXjlIVVxevh38vTqt+mSovpp4Pj1DTYc2fTAu3JrErDaRK6ceK68qMpTDkI27LWu KisFJrCZt/ExHk59165UxO2MzC1AKJVZUU5g0jgjmuaekWKG85QGmsz9Fo4cuMfVXh POgWn5yfavniA== From: Mario Limonciello To: Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v9 03/13] x86/msr-index: define AMD heterogeneous CPU related MSR Date: Tue, 22 Apr 2025 20:46:21 -0500 Message-ID: <20250423014631.3224338-4-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250423014631.3224338-1-superm1@kernel.org> References: <20250423014631.3224338-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan Introduces new MSR registers for AMD hardware feedback support. These registers enable the system to provide workload classification and configuration capabilities. Reviewed-by: Gautham R. Shenoy Signed-off-by: Perry Yuan Signed-off-by: Mario Limonciello --- arch/x86/include/asm/msr-index.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index ac21dc19dde21..0c761033aa714 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -724,6 +724,11 @@ #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 +/* AMD Hardware Feedback Support MSRs */ +#define AMD_WORKLOAD_CLASS_CONFIG 0xc0000500 +#define AMD_WORKLOAD_CLASS_ID 0xc0000501 +#define AMD_WORKLOAD_HRST 0xc0000502 + /* AMD Last Branch Record MSRs */ #define MSR_AMD64_LBR_SELECT 0xc000010e