Message ID | 20250410-dt-cpu-schema-v2-2-63d7dc9ddd0a@kernel.org |
---|---|
State | New |
Headers | show |
Series | Arm cpu schema clean-ups | expand |
On 4/10/25 08:47, Rob Herring (Arm) wrote: > There's no need include the CPU number in the L2 cache node names as > the names are local to the CPU nodes. The documented node name is > also just "l2-cache". > > Signed-off-by: Rob Herring (Arm) <robh@kernel.org> > Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Not sure how you had intended for me to pick up that patch without copying the maintainers. Applied nonetheless, thanks!
On Fri, Apr 11, 2025 at 6:37 PM Florian Fainelli <f.fainelli@gmail.com> wrote: > > On 4/10/25 08:47, Rob Herring (Arm) wrote: > > There's no need include the CPU number in the L2 cache node names as > > the names are local to the CPU nodes. The documented node name is > > also just "l2-cache". > > > > Signed-off-by: Rob Herring (Arm) <robh@kernel.org> > > Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> > > Not sure how you had intended for me to pick up that patch without > copying the maintainers. Looks like there is a problem in MAINTAINERS. This matches what b4 runs: $ git show cca91c99fe14 | scripts/get_maintainer.pl --nogit --nogit-fallback --nogit-chief-penguins --norolestats Rob Herring <robh@kernel.org> Krzysztof Kozlowski <krzk+dt@kernel.org> Conor Dooley <conor+dt@kernel.org> devicetree@vger.kernel.org linux-kernel@vger.kernel.org > Applied nonetheless, thanks! Thanks. Rob
diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi index 9e610a89a337..ad0cac8e4444 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -64,7 +64,7 @@ cpu0: cpu@0 { i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set next-level-cache = <&l2_cache_l0>; - l2_cache_l0: l2-cache-l0 { + l2_cache_l0: l2-cache { compatible = "cache"; cache-size = <0x80000>; cache-line-size = <64>; @@ -88,7 +88,7 @@ cpu1: cpu@1 { i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set next-level-cache = <&l2_cache_l1>; - l2_cache_l1: l2-cache-l1 { + l2_cache_l1: l2-cache { compatible = "cache"; cache-size = <0x80000>; cache-line-size = <64>; @@ -112,7 +112,7 @@ cpu2: cpu@2 { i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set next-level-cache = <&l2_cache_l2>; - l2_cache_l2: l2-cache-l2 { + l2_cache_l2: l2-cache { compatible = "cache"; cache-size = <0x80000>; cache-line-size = <64>; @@ -136,7 +136,7 @@ cpu3: cpu@3 { i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set next-level-cache = <&l2_cache_l3>; - l2_cache_l3: l2-cache-l3 { + l2_cache_l3: l2-cache { compatible = "cache"; cache-size = <0x80000>; cache-line-size = <64>;