From patchwork Thu Feb 27 10:59:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 869193 Received: from mail-m1973193.qiye.163.com (mail-m1973193.qiye.163.com [220.197.31.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E3251DB122; Thu, 27 Feb 2025 11:00:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740654038; cv=none; b=Gh69ZhCjySB78Lsl1m6NNQDdYzo7mO3HBKup6DRy8ZLvV8uSFXZWpmRBhBeYtds7kNvGaP5QBm/3xLKKjSEZZcMfmLfDDLL5fUMMHshaDjx/PAaJpYNmRtjgpIW7gLu5PdQuLTofxeCIZBEsddbO1ydM+CeDaVdgkaH5vY//HdM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740654038; c=relaxed/simple; bh=cD3y5ZhdpenKn5hoKiicTRrOcaIRHrcfAFa8VdSyc0w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ibDmFLMKe+HR8mH+bgRLXBXnIuQjZX+jvvl+mS1FPHq2UT8hcKcPGhOPrfynuJnFlueeSgclMu/clSMr+OIj1HFelsS/nvfH94R+9N9uhhNkp445Z8SevhNzhtNA13rQoFIcWhChma0UaHGXpTc6TSEywTX8nysNLBw3CgLkG6I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=Txix2qS2; arc=none smtp.client-ip=220.197.31.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="Txix2qS2" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id c6596ac9; Thu, 27 Feb 2025 19:00:26 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , Finley Xiao , Krzysztof Kozlowski , linux-pm@vger.kernel.org, Jonathan Cameron , Detlev Casanova , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Ulf Hansson Subject: [PATCH v3 2/2] soc: rockchip: power-domain: add power domain support for rk3562 Date: Thu, 27 Feb 2025 18:59:57 +0800 Message-Id: <20250227105957.2341107-3-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250227105957.2341107-1-kever.yang@rock-chips.com> References: <20250227105957.2341107-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGk0ZQ1YaT00dSx8eGU5OT0hWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ X-HM-Tid: 0a9547109f3203afkunmc6596ac9 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6NRw6NBw*KTINTg0BAiICOTIa EhwKCTVVSlVKTE9LTU5PS0lMTUJCVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFPT0lMNwY+ DKIM-Signature: a=rsa-sha256; b=Txix2qS21u7XOR6rtQdlq1PXcupaV8OhxHDt0ZzGNQe0tZU/WaBCglnB5ST5JX1Ve1TCtvJXSNtVhRWCUfM8kDyY+cX7ysamMjFWNtShxyDQnerEM8Cv/sIEgWJxiVhFl0nhtU12FHeEjQrXiNkcHhGWkW55L3CUfabm6PWVFbI=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=DKX8ERULlKOlqmEzPMDQ7tcuj/pXzM/HFpRfsyeTQqQ=; h=date:mime-version:subject:message-id:from; This driver is modified to support RK3562 SoC. Add support to ungate clk. Add support to shut down memory for rk3562. Signed-off-by: Finley Xiao Signed-off-by: Kever Yang --- Changes in v3: None Changes in v2: - update the header name drivers/pmdomain/rockchip/pm-domains.c | 48 +++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c index cb0f93800138..d05ec0a009a0 100644 --- a/drivers/pmdomain/rockchip/pm-domains.c +++ b/drivers/pmdomain/rockchip/pm-domains.c @@ -2,7 +2,7 @@ /* * Rockchip Generic power domain support. * - * Copyright (c) 2015 ROCKCHIP, Co. Ltd. + * Copyright (c) 2015 Rockchip Electronics Co., Ltd. */ #include @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -129,6 +130,20 @@ struct rockchip_pmu { .active_wakeup = wakeup, \ } +#define DOMAIN_M_G_SD(_name, pwr, status, req, idle, ack, g_mask, mem, wakeup, keepon) \ +{ \ + .name = _name, \ + .pwr_w_mask = (pwr) << 16, \ + .pwr_mask = (pwr), \ + .status_mask = (status), \ + .req_w_mask = (req) << 16, \ + .req_mask = (req), \ + .idle_mask = (idle), \ + .ack_mask = (ack), \ + .clk_ungate_mask = (g_mask), \ + .active_wakeup = wakeup, \ +} + #define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup) \ { \ .name = _name, \ @@ -194,6 +209,9 @@ struct rockchip_pmu { #define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ DOMAIN(name, pwr, status, req, req, req, wakeup) +#define DOMAIN_RK3562(name, pwr, req, g_mask, mem, wakeup) \ + DOMAIN_M_G_SD(name, pwr, pwr, req, req, req, g_mask, mem, wakeup, false) + #define DOMAIN_RK3568(name, pwr, req, wakeup) \ DOMAIN_M(name, pwr, pwr, req, req, req, wakeup) @@ -1130,6 +1148,18 @@ static const struct rockchip_domain_info rk3399_pm_domains[] = { [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), }; +static const struct rockchip_domain_info rk3562_pm_domains[] = { + /* name pwr req g_mask mem wakeup */ + [RK3562_PD_GPU] = DOMAIN_RK3562("gpu", BIT(0), BIT(1), BIT(1), 0, false), + [RK3562_PD_NPU] = DOMAIN_RK3562("npu", BIT(1), BIT(2), BIT(2), 0, false), + [RK3562_PD_VDPU] = DOMAIN_RK3562("vdpu", BIT(2), BIT(6), BIT(6), 0, false), + [RK3562_PD_VEPU] = DOMAIN_RK3562("vepu", BIT(3), BIT(7), BIT(7) | BIT(3), 0, false), + [RK3562_PD_RGA] = DOMAIN_RK3562("rga", BIT(4), BIT(5), BIT(5) | BIT(4), 0, false), + [RK3562_PD_VI] = DOMAIN_RK3562("vi", BIT(5), BIT(3), BIT(3), 0, false), + [RK3562_PD_VO] = DOMAIN_RK3562("vo", BIT(6), BIT(4), BIT(4), 16, false), + [RK3562_PD_PHP] = DOMAIN_RK3562("php", BIT(7), BIT(8), BIT(8), 0, false), +}; + static const struct rockchip_domain_info rk3568_pm_domains[] = { [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false), [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false), @@ -1331,6 +1361,18 @@ static const struct rockchip_pmu_info rk3399_pmu = { .domain_info = rk3399_pm_domains, }; +static const struct rockchip_pmu_info rk3562_pmu = { + .pwr_offset = 0x210, + .status_offset = 0x230, + .req_offset = 0x110, + .idle_offset = 0x128, + .ack_offset = 0x120, + .clk_ungate_offset = 0x140, + + .num_domains = ARRAY_SIZE(rk3562_pm_domains), + .domain_info = rk3562_pm_domains, +}; + static const struct rockchip_pmu_info rk3568_pmu = { .pwr_offset = 0xa0, .status_offset = 0x98, @@ -1429,6 +1471,10 @@ static const struct of_device_id rockchip_pm_domain_dt_match[] = { .compatible = "rockchip,rk3399-power-controller", .data = (void *)&rk3399_pmu, }, + { + .compatible = "rockchip,rk3562-power-controller", + .data = (void *)&rk3562_pmu, + }, { .compatible = "rockchip,rk3568-power-controller", .data = (void *)&rk3568_pmu,