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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D8.mail.protection.outlook.com (10.167.241.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8230.7 via Frontend Transport; Sun, 8 Dec 2024 06:31:00 +0000 Received: from AUS-P9-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Sun, 8 Dec 2024 00:30:57 -0600 From: Mario Limonciello To: "Gautham R . Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH v2 10/16] cpufreq/amd-pstate: Move limit updating code Date: Sun, 8 Dec 2024 00:30:25 -0600 Message-ID: <20241208063031.3113-11-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241208063031.3113-1-mario.limonciello@amd.com> References: <20241208063031.3113-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D8:EE_|CY8PR12MB7340:EE_ X-MS-Office365-Filtering-Correlation-Id: 56f42a17-c6d4-41ef-5b22-08dd1751e1da X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|36860700013|1800799024|376014; X-Microsoft-Antispam-Message-Info: Q01gqTUfCmg4kkC4KZVzm0UpEKOhOKxmZDPj6aKB2QT8BxogqBXcRRcjeycK1uHgEIEtvs6BjfOyU6crY3syu+w8vb7OAv0tLKIaY/+DWIjfN1pblq/bJn0SVefM7jTFTiGu4/poH5/oJdFEbwolMCyMY2qrlnHtG0kXeAX6PT5AUDl7XqWazMkdBZne6vZQgs4vCaHilpgBC+O4GqQyTuoB3djWGCsb2kOr4ESJT2qQu0hIu4cgl1vN1Jj2eJXLI5jUD9j/yFt9BrSpcpTXR7Ch/kM62lsiBuZLv5PBeE1Dv//2MPWB7DF/LM3WPcMn3Z/xtJQGcj4l74gxv0QDX6yRRiUoHuPgzlZ0nBElevrZQe0R1xv2owSpLobLnLo0k+TYss0iL5q9ZEyUv3jnuO01RtHKppm5xWiGCsSnXaOehi+WVHoUi2FuUo0W4WykZjCwU8dkOqd2BOYBXzphhfbScG6OX/jXuFa1v2BNitbIomIcZm//ueaoHeQGAlK1S3rM99RtJsQH6yMNxOiQItBKGrUU6EPU4J4clsTWCduTJ5HyYTqECHvo7cG21iApfdqBHDI0nNTek1OyWJPY1yopAvEYdzZJJcU90Sug9yVAk2d/TveCOlkaW0WbPN4x5UvMpFBir3qjiAkMPen0HQCK4jwa5IYiM9pYV/sPm2MPE8YE1XUHlIFFPTHSWg9UrtOIHCqAKoD0sqv4XiQOu4eRlo3E9wZY3eqffsn0bvk9CjMl/l9WQumcqoJuqu3a3i+2kJ2HCM+nsBN+Ppi94YZ8MOY3Bjws6BKojW9QK9GuDMixOhZeIJpbvya+aXCaZN1iyicDjNw8ASbYI8gMWR2fjwAqLbLHAscnuLWRq+ma+/bkz32CRv9qtwCVYJs6Ewp+6ZUZoA/UkDoyh9N2Gkwwuz203QocFmRoikWzrLiiGgDx5R1gZcjVA6dKeYueGSvu1vBUZsAKj3kav5vWXDAe76nReC88Zx0rvIH2l5W19ANxNstfqYXyjIAtvXw20chDlOsDLYN9XNUTt+iGxPzdeya1zwvRZx+naQZ3bbiW8d+QlHQnpsS9WPJgMnoQg+oOEtMk9MHLam+mHTFkhSuEoMVHdEAnQQZIyL0XGZCEILd+PBnttxX2wAWgFCpA4RKGbxuozr+DIAlCEiJD04/o/+HJxIQ57CL12yKp06v34Tfhj57+ysoZJzd8EKF7LAanlkB0lEDRXWHaSYWjWKcE/SSWiJ5F+pvNXEzsw47otMTNbgTyRZ+YJcFJIcG+v14lL/afwr6CueXpvw46UKLL+5DGjaOnIQy6cjaRuHcY9p75kYO3YD9AFTqpsko5qRmX2DH7tU1nSeyM9flJb1EJq0uDz2lyw8pGbuDIlRn8IKcg2zNa0Sa7zIm5PY51SKEMnHm0QU1Uz5nXHGEYFIiQfjCYp2aofOOU7iyjBG1cMjTqdtEYSXzahxPdtQgE X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Dec 2024 06:31:00.3733 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 56f42a17-c6d4-41ef-5b22-08dd1751e1da X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7340 The limit updating code in amd_pstate_epp_update_limit() should not only apply to EPP updates. Move it to amd_pstate_update_min_max_limit() so other callers can benefit as well. With this move it's not necessary to have clamp_t calls anymore because the verify callback is called when setting limits. Reviewed-by: Gautham R. Shenoy Signed-off-by: Mario Limonciello --- v2: * Drop lowest_perf variable --- drivers/cpufreq/amd-pstate.c | 28 +++++----------------------- 1 file changed, 5 insertions(+), 23 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 3a3df67c096d5..dc3c45b6f5103 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -537,10 +537,6 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, u32 nominal_perf = READ_ONCE(cpudata->nominal_perf); u64 value = prev; - min_perf = clamp_t(unsigned long, min_perf, cpudata->min_limit_perf, - cpudata->max_limit_perf); - max_perf = clamp_t(unsigned long, max_perf, cpudata->min_limit_perf, - cpudata->max_limit_perf); des_perf = clamp_t(unsigned long, des_perf, min_perf, max_perf); max_freq = READ_ONCE(cpudata->max_limit_freq); @@ -607,7 +603,7 @@ static int amd_pstate_verify(struct cpufreq_policy_data *policy_data) static int amd_pstate_update_min_max_limit(struct cpufreq_policy *policy) { - u32 max_limit_perf, min_limit_perf, lowest_perf, max_perf, max_freq; + u32 max_limit_perf, min_limit_perf, max_perf, max_freq; struct amd_cpudata *cpudata = policy->driver_data; max_perf = READ_ONCE(cpudata->highest_perf); @@ -615,12 +611,8 @@ static int amd_pstate_update_min_max_limit(struct cpufreq_policy *policy) max_limit_perf = div_u64(policy->max * max_perf, max_freq); min_limit_perf = div_u64(policy->min * max_perf, max_freq); - lowest_perf = READ_ONCE(cpudata->lowest_perf); - if (min_limit_perf < lowest_perf) - min_limit_perf = lowest_perf; - - if (max_limit_perf < min_limit_perf) - max_limit_perf = min_limit_perf; + if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) + min_limit_perf = min(cpudata->nominal_perf, max_limit_perf); WRITE_ONCE(cpudata->max_limit_perf, max_limit_perf); WRITE_ONCE(cpudata->min_limit_perf, min_limit_perf); @@ -1562,28 +1554,18 @@ static void amd_pstate_epp_cpu_exit(struct cpufreq_policy *policy) static int amd_pstate_epp_update_limit(struct cpufreq_policy *policy) { struct amd_cpudata *cpudata = policy->driver_data; - u32 max_perf, min_perf; u64 value; s16 epp; - max_perf = READ_ONCE(cpudata->highest_perf); - min_perf = READ_ONCE(cpudata->lowest_perf); amd_pstate_update_min_max_limit(policy); - max_perf = clamp_t(unsigned long, max_perf, cpudata->min_limit_perf, - cpudata->max_limit_perf); - min_perf = clamp_t(unsigned long, min_perf, cpudata->min_limit_perf, - cpudata->max_limit_perf); value = READ_ONCE(cpudata->cppc_req_cached); - if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) - min_perf = min(cpudata->nominal_perf, max_perf); - value &= ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK | AMD_CPPC_DES_PERF_MASK); - value |= FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, max_perf); + value |= FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, cpudata->max_limit_perf); value |= FIELD_PREP(AMD_CPPC_DES_PERF_MASK, 0); - value |= FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, min_perf); + value |= FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, cpudata->min_limit_perf); /* Get BIOS pre-defined epp value */ epp = amd_pstate_get_epp(cpudata, value);