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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SA2PEPF000015CC.mail.protection.outlook.com (10.167.241.202) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8230.7 via Frontend Transport; Sat, 30 Nov 2024 14:07:56 +0000 Received: from AUS-P9-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Sat, 30 Nov 2024 08:07:53 -0600 From: Mario Limonciello To: Borislav Petkov CC: Thomas Gleixner , Ingo Molnar , "Dave Hansen" , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "H . Peter Anvin" , "Rafael J . Wysocki" , "Gautham R . Shenoy" , Mario Limonciello , Perry Yuan , Brijesh Singh , Peter Zijlstra , Li RongQing , "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "open list:ACPI" , "open list:AMD PSTATE DRIVER" , Pawan Gupta Subject: [PATCH v7 09/12] x86/process: Clear hardware feedback history for AMD processors Date: Sat, 30 Nov 2024 08:07:00 -0600 Message-ID: <20241130140703.557-10-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241130140703.557-1-mario.limonciello@amd.com> References: <20241130140703.557-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CC:EE_|BL1PR12MB5707:EE_ X-MS-Office365-Filtering-Correlation-Id: 87e5fbaa-fb8f-4c32-d6aa-08dd11486389 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|82310400026|7416014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: 20oCt3Wr4P6l9wML8eZYtw3eD8/qfi9MoaPa2+OdKarpd1TX/AL1VGeanB5sEusKqbywNDmmmdbUAG/r4BmPGQ8Jwi/Pn/43nFUn8KD/ybJGfvXhGThK5SKfZTIlj7BimrTZOWtJ0hS1yNq6w6K72JjabpWZtj6X+0bMllI3MUhZJyZhCOaRuGlPAm1saEu9hJI15Y7U+lqsnXuP39OA+ILvI0QKxVescJ/Ds0/pPS2lm6NcB4CUdIwlqKNdszzh9Ad2tFQuBbbswspuJgOlVoosD3r4Oqmei9SEL5/w0XCNj3Pd7RBwEiDyXtfhnTfnqxAzpYY+R0C05ed7k0mZ1DxnYZsG0KKsoU/NPZheCJbCixlepWpVnOSH9+jAlMcU6e+YLSHJpwU6FqLsOy7VJctMQk+n9YDJkcRkZZr/VhbwUe3GdFOllh7+GPi39xxby3le12wzwIXgDnGdL1tSHwCyPbORvyPq1lmtSR8jxGrp+u+OtZke0PD9dAwBm3PT4isEWlZ7/MEbhMeUT0gd+9koT68q/1PCh++KddyCSj0XiE0TH6saJuZrTUK3d/F5IUaP58Wv3s+Hu0AYiwnkO9vC8/Js6QyxmrQUsKILAbpscm0iVFMcWLaPchAZH/FS/knTJaBKW1VSlHsNxm/H1u5ccjdXmAB72wTHBNI/p4qiQB8bTP59SC9O+t6J6mgXuM8LQ5ZI0O706KQjPAujO+WKR53XTg7a5oohJyxDSmAIkHFzG7ODvpcHfE9GYNW6MLaFCN3zQvvMHJyYmtZURPFz4AjC5ZyO0cKKszOgVFiB0ar5bEX49h4vaNN3zbb6FpzIn3MEczhj8LSqTV5YOqD/QfEJo2hqt7XKDihFt+04pUw5wTlxQWONgC/S+poJy391coJ7GJJTBeuWg98zlfCNN4wjqLjrlurAG4AjRljaM7Ckpbm0XA5Mj5mrCjreYOcZgSJQ/TvVr2bBOK3DQe33U1L0L8NEgZ0S2+lqKl4rh84LdRQqSILn5dGmRTnOmF9/NvEPARkPu9QSZ7ZNt9jaENvbh+S81AwUhLBEkPtCiGQuCYuj3ZNbcFwYn5w6RG9p7mMnpQxk3tYPpklrEXqX3hr3wiOWrnpR+ttD6u90QqGsfPnex7x6PHbN92llim6MGgNn61jCBS4kWtVi3e1gWjok/+I+T+Pwy6wnFHRm4KkitcCgSH/hnE1n4455Dubj2q/YcGko9/wKDU9T58OBgAnGCBmXDfnmigJmxYAOVtk2FNIr5CwbAY+N0rD6V09FvT2BosNXedevnQg6kFQGx1vJ8eoSMsGLQi/s4Vc74tK7egni8XJH4SZPAfxzasrx9jcivRM38d0PvxoTdRI2+Lf0dxblFJqmOily7fONVoL82+En2Q6Vlub8iR8soqLln8ob11k6j/xL8iuGLl+DH593qZkVk8cZvj3x53MDsgude9fe6NjJnehOZnmf X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(376014)(82310400026)(7416014)(36860700013)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2024 14:07:56.0836 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 87e5fbaa-fb8f-4c32-d6aa-08dd11486389 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CC.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5707 From: Perry Yuan Incorporate a mechanism within the context switching code to reset the hardware history for AMD processors. Specifically, when a task is switched in, the class ID was read and reset the hardware workload classification history of CPU firmware and then it start to trigger workload classification for the next running thread. Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- arch/x86/kernel/process_32.c | 4 ++++ arch/x86/kernel/process_64.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c index 0917c7f25720b..0bb6391b9089b 100644 --- a/arch/x86/kernel/process_32.c +++ b/arch/x86/kernel/process_32.c @@ -213,6 +213,10 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) /* Load the Intel cache allocation PQR MSR. */ resctrl_sched_in(next_p); + /* Reset hw history on AMD CPUs */ + if (cpu_feature_enabled(X86_FEATURE_AMD_WORKLOAD_CLASS)) + wrmsrl(AMD_WORKLOAD_HRST, 0x1); + return prev_p; } diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 226472332a70d..371e0e8f987fa 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -709,6 +709,10 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) /* Load the Intel cache allocation PQR MSR. */ resctrl_sched_in(next_p); + /* Reset hw history on AMD CPUs */ + if (cpu_feature_enabled(X86_FEATURE_AMD_WORKLOAD_CLASS)) + wrmsrl(AMD_WORKLOAD_HRST, 0x1); + return prev_p; }