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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN2PEPF00004FBE.mail.protection.outlook.com (10.167.243.184) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8093.14 via Frontend Transport; Fri, 25 Oct 2024 17:15:35 +0000 Received: from AUS-P9-MLIMONCI.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 25 Oct 2024 12:15:33 -0500 From: Mario Limonciello To: Borislav Petkov CC: Thomas Gleixner , Ingo Molnar , "Dave Hansen" , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "H . Peter Anvin" , "Rafael J . Wysocki" , "Gautham R . Shenoy" , Mario Limonciello , Perry Yuan , Brijesh Singh , Peter Zijlstra , Li RongQing , "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "open list:ACPI" , "open list:AMD PSTATE DRIVER" , Pawan Gupta Subject: [PATCH v4 4/5] x86/cpu: Add CPU type to struct cpuinfo_topology Date: Fri, 25 Oct 2024 12:14:58 -0500 Message-ID: <20241025171459.1093-5-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025171459.1093-1-mario.limonciello@amd.com> References: <20241025171459.1093-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FBE:EE_|PH0PR12MB7981:EE_ X-MS-Office365-Filtering-Correlation-Id: 0f9d2cd3-ed5c-4fbc-205f-08dcf518a3ea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|7416014|376014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: j1LI5AMMUrSVMvlLi0iYwGX+CPJbTZWJyfqSZXjLlz8M3dFpfxdD0s3bhwt4jzEr+9XSREs+Nf8Yx5tHdCkqeFfKzmetDnJi70os5yn3v+MB17ckarLanDEzRJK+tZTn4wKGCu16ouQilyzgTqsC07tU/jN36hAbGKb+seTgK+TrOzkEN+h+tF3tiEGzpibRssN6SzKCY+EoyAJDP9NZtk9Rx9vqv9BRY1sII6skHV1//SNs6JYbmFUGVhrEJ7MQ0IMWh/sVzlJbf4FKoD0KshCscO+VPdGGKk6TGg/6l+e+bBOTc8+iLfYnXVQImb40t0rYfP+3ZzyJR08PX7i8FkpOF7SeZQkoZUs8BZVAcIYlA8SEBzx0B4GogpkutAnygvJs3UYJxxl3mtzaSt/MrC9g8Q3GJB+nWelRSTLMSuxydRywFPBK9RI2lMxSoy74doW9Ua0PDQaLuEpR2xsve3hBzBKoK6QEgFlhw7/n/tu22Wbvusy6n3r+1yN/RdKljUjwDpMuMKGhWPC1/h8V60kzTx66xb4NC0iDnFYDkqUhMWGXjpkdb6wDPuGfurDnw2l7SLqrmvRAuVIXPvYkTfCvInS74GGbQ3RwqDAZ8dhUpUWE4D1fnf8Pgn0EZ+MJO3bf5d7j9tJ6EAatAR5NWForfT9lLijrWHKrgq3v5GqtnTlHal38wYTzi2IvsbYe4f3Au0IgyuAhANCsI9hjP0tTR2Cc/qJczRlnOQ0UF1AYCRsc6ldv4FevLtkY8/hTUilw9VlluvSdN+iXqL41dextk97rUV3G175cL/+ZgeulZp2BcF33bPMKNY9r8AcQ/ioGcpcXmO3dYTDvCgDjGs46uReGuMW3zvqMkdLa12k1hAvKpxvFE1NQuOO3jkwIS+rtg1wOc8isiYtpqPLgWDkRwW7dTmAoKusaHR6Djlhmfpcag9Z9ZKJNVdBxe0NZsYVJx8lXrQTmoTnOLDAOPEUyQWX7U8XYRoi/Gwfe8aj8STT0qSuTnQY73tPALF+hqwTpi0F6HlgS5c3a+5o+bJOJ4XLG3k2gRUqoa+YSLbGT+xiW1XpMEyn4syx46f+n4VjjbM4/AKk/lscmJLIDOrD3Cigmv6mmGJA0Ldclj0KffAYozKn3fyLtJ8k1/+UDLN5yyUM8lwYtQjkwS5WasGuROSPJ4z5kPDUL1jYR4774Yw9EpPCBNle3BZmjPWifOjyzogpQdAdtLANhIDEEXBc3w/Fmsv3w6YG02JfacnxsTemGxkk5EUkggspUvRZ6S+3st0KiHudLExFT/ap2xp8AojyudpBZNcf7wJTpW5iZ404q5txzD0Bbb9gqTf41OCPAThvE4glFRc/a9whe5epoEY2IlD3fS3UOsvIAN0xzubfCwmd+0PzfSz0m2gPDKMPMGko68BPW3hOXgKAZxw== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(7416014)(376014)(36860700013)(82310400026)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 17:15:35.7037 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0f9d2cd3-ed5c-4fbc-205f-08dcf518a3ea X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBE.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7981 From: Pawan Gupta Sometimes it is required to take actions based on if a CPU is a performance or efficiency core. As an example, intel_pstate driver uses the Intel core-type to determine CPU scaling. Also, some CPU vulnerabilities only affect a specific CPU type, like RFDS only affects Intel Atom. Hybrid systems that have variants P+E, P-only(Core) and E-only(Atom), it is not straightforward to identify which variant is affected by a type specific vulnerability. Such processors do have CPUID field that can uniquely identify them. Like, P+E, P-only and E-only enumerates CPUID.1A.CORE_TYPE identification, while P+E additionally enumerates CPUID.7.HYBRID. Based on this information, it is possible for boot CPU to identify if a system has mixed CPU types. Add a new field hw_cpu_type to struct cpuinfo_topology that stores the hardware specific CPU type. This saves the overhead of IPIs to get the CPU type of a different CPU. CPU type is populated early in the boot process, before vulnerabilities are enumerated. Acked-by: Dave Hansen Signed-off-by: Pawan Gupta Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v3->v4: * Drop generic from function name (Boris) * Pick up tag v2->v3: * Remove a bunch of boilerplate code * Convert to showing string in debugfs * Rename to get_topology_generic_cpu_type/get_topology_cpu_type_name * Add Intel definitions to intel-family.h --- arch/x86/include/asm/intel-family.h | 6 +++++ arch/x86/include/asm/processor.h | 18 ++++++++++++++ arch/x86/include/asm/topology.h | 9 +++++++ arch/x86/kernel/cpu/debugfs.c | 1 + arch/x86/kernel/cpu/topology_amd.c | 3 +++ arch/x86/kernel/cpu/topology_common.c | 34 +++++++++++++++++++++++++++ 6 files changed, 71 insertions(+) diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index 1a42f829667a3..7367644720484 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -183,4 +183,10 @@ /* Family 19 */ #define INTEL_PANTHERCOVE_X IFM(19, 0x01) /* Diamond Rapids */ +/* CPU core types */ +enum intel_cpu_type { + INTEL_CPU_TYPE_ATOM = 0x20, + INTEL_CPU_TYPE_CORE = 0x40, +}; + #endif /* _ASM_X86_INTEL_FAMILY_H */ diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 4a686f0e5dbf6..c0975815980c8 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -105,6 +105,24 @@ struct cpuinfo_topology { // Cache level topology IDs u32 llc_id; u32 l2c_id; + + // Hardware defined CPU-type + union { + u32 cpu_type; + struct { + // CPUID.1A.EAX[23-0] + u32 intel_native_model_id :24; + // CPUID.1A.EAX[31-24] + u32 intel_type :8; + }; + struct { + // CPUID 0x80000026.EBX + u32 amd_num_processors :16, + amd_power_eff_ranking :8, + amd_native_model_id :4, + amd_type :4; + }; + }; }; struct cpuinfo_x86 { diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h index aef70336d6247..9f9376db64e32 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -114,6 +114,12 @@ enum x86_topology_domains { TOPO_MAX_DOMAIN, }; +enum x86_topology_cpu_type { + TOPO_CPU_TYPE_PERFORMANCE, + TOPO_CPU_TYPE_EFFICIENCY, + TOPO_CPU_TYPE_UNKNOWN, +}; + struct x86_topology_system { unsigned int dom_shifts[TOPO_MAX_DOMAIN]; unsigned int dom_size[TOPO_MAX_DOMAIN]; @@ -149,6 +155,9 @@ extern unsigned int __max_threads_per_core; extern unsigned int __num_threads_per_package; extern unsigned int __num_cores_per_package; +const char *get_topology_cpu_type_name(struct cpuinfo_x86 *c); +enum x86_topology_cpu_type get_topology_cpu_type(struct cpuinfo_x86 *c); + static inline unsigned int topology_max_packages(void) { return __max_logical_packages; diff --git a/arch/x86/kernel/cpu/debugfs.c b/arch/x86/kernel/cpu/debugfs.c index 3baf3e4358347..10719aba62768 100644 --- a/arch/x86/kernel/cpu/debugfs.c +++ b/arch/x86/kernel/cpu/debugfs.c @@ -22,6 +22,7 @@ static int cpu_debug_show(struct seq_file *m, void *p) seq_printf(m, "die_id: %u\n", c->topo.die_id); seq_printf(m, "cu_id: %u\n", c->topo.cu_id); seq_printf(m, "core_id: %u\n", c->topo.core_id); + seq_printf(m, "cpu_type: %s\n", get_topology_cpu_type_name(c)); seq_printf(m, "logical_pkg_id: %u\n", c->topo.logical_pkg_id); seq_printf(m, "logical_die_id: %u\n", c->topo.logical_die_id); seq_printf(m, "llc_id: %u\n", c->topo.llc_id); diff --git a/arch/x86/kernel/cpu/topology_amd.c b/arch/x86/kernel/cpu/topology_amd.c index 7d476fa697ca5..03b3c9c3a45e2 100644 --- a/arch/x86/kernel/cpu/topology_amd.c +++ b/arch/x86/kernel/cpu/topology_amd.c @@ -182,6 +182,9 @@ static void parse_topology_amd(struct topo_scan *tscan) if (cpu_feature_enabled(X86_FEATURE_TOPOEXT)) has_topoext = cpu_parse_topology_ext(tscan); + if (cpu_feature_enabled(X86_FEATURE_AMD_HETEROGENEOUS_CORES)) + tscan->c->topo.cpu_type = cpuid_ebx(0x80000026); + if (!has_topoext && !parse_8000_0008(tscan)) return; diff --git a/arch/x86/kernel/cpu/topology_common.c b/arch/x86/kernel/cpu/topology_common.c index 9a6069e7133c9..8277c64f88dbf 100644 --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -3,6 +3,7 @@ #include +#include #include #include #include @@ -27,6 +28,36 @@ void topology_set_dom(struct topo_scan *tscan, enum x86_topology_domains dom, } } +enum x86_topology_cpu_type get_topology_cpu_type(struct cpuinfo_x86 *c) +{ + if (c->x86_vendor == X86_VENDOR_INTEL) { + switch (c->topo.intel_type) { + case INTEL_CPU_TYPE_ATOM: return TOPO_CPU_TYPE_EFFICIENCY; + case INTEL_CPU_TYPE_CORE: return TOPO_CPU_TYPE_PERFORMANCE; + } + } + if (c->x86_vendor == X86_VENDOR_AMD) { + switch (c->topo.amd_type) { + case 0: return TOPO_CPU_TYPE_PERFORMANCE; + case 1: return TOPO_CPU_TYPE_EFFICIENCY; + } + } + + return TOPO_CPU_TYPE_UNKNOWN; +} + +const char *get_topology_cpu_type_name(struct cpuinfo_x86 *c) +{ + switch (get_topology_cpu_type(c)) { + case TOPO_CPU_TYPE_PERFORMANCE: + return "performance"; + case TOPO_CPU_TYPE_EFFICIENCY: + return "efficiency"; + default: + return "unknown"; + } +} + static unsigned int __maybe_unused parse_num_cores_legacy(struct cpuinfo_x86 *c) { struct { @@ -87,6 +118,7 @@ static void parse_topology(struct topo_scan *tscan, bool early) .cu_id = 0xff, .llc_id = BAD_APICID, .l2c_id = BAD_APICID, + .cpu_type = TOPO_CPU_TYPE_UNKNOWN, }; struct cpuinfo_x86 *c = tscan->c; struct { @@ -132,6 +164,8 @@ static void parse_topology(struct topo_scan *tscan, bool early) case X86_VENDOR_INTEL: if (!IS_ENABLED(CONFIG_CPU_SUP_INTEL) || !cpu_parse_topology_ext(tscan)) parse_legacy(tscan); + if (c->cpuid_level >= 0x1a) + c->topo.cpu_type = cpuid_eax(0x1a); break; case X86_VENDOR_HYGON: if (IS_ENABLED(CONFIG_CPU_SUP_HYGON))