diff mbox series

[2/2] cpufreq: ti-cpufreq: Remove revision offsets in AM62 family

Message ID 20240930-b4-ti-cpufreq-am62-quirk-v1-2-b5e04f0f899b@ti.com
State New
Headers show
Series [1/2] cpufreq: ti-cpufreq: Allow backward compatibility for efuse syscon | expand

Commit Message

Dhruva Gole Sept. 30, 2024, 9:32 a.m. UTC 
With the Silicon revision being taken directly from socinfo, there's no
longer any need for reading any SOC register for revision from this driver.
Hence, we do not require any rev_offset for AM62 family of devices.

Signed-off-by: Dhruva Gole <d-gole@ti.com>
---
 drivers/cpufreq/ti-cpufreq.c | 3 ---
 1 file changed, 3 deletions(-)
diff mbox series

Patch

diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c
index 7014cebb41e3490cadd14834e0c3e057419f2abb..5a5147277cd0ab03031926cd62f6ba61aea78512 100644
--- a/drivers/cpufreq/ti-cpufreq.c
+++ b/drivers/cpufreq/ti-cpufreq.c
@@ -318,7 +318,6 @@  static struct ti_cpufreq_soc_data am625_soc_data = {
 	.efuse_offset = 0x0018,
 	.efuse_mask = 0x07c0,
 	.efuse_shift = 0x6,
-	.rev_offset = 0x0014,
 	.multi_regulator = false,
 	.quirks = TI_QUIRK_SYSCON_IS_SINGLE_REG,
 };
@@ -328,7 +327,6 @@  static struct ti_cpufreq_soc_data am62a7_soc_data = {
 	.efuse_offset = 0x0,
 	.efuse_mask = 0x07c0,
 	.efuse_shift = 0x6,
-	.rev_offset = 0x0014,
 	.multi_regulator = false,
 };
 
@@ -337,7 +335,6 @@  static struct ti_cpufreq_soc_data am62p5_soc_data = {
 	.efuse_offset = 0x0,
 	.efuse_mask = 0x07c0,
 	.efuse_shift = 0x6,
-	.rev_offset = 0x0014,
 	.multi_regulator = false,
 };