diff mbox series

[v2,1/3] riscv: Add csr_read/write_hi_lo support

Message ID 20240926065422.226518-2-nick.hu@sifive.com
State New
Headers show
Series Support SSTC while PM operations | expand

Commit Message

Nick Hu Sept. 26, 2024, 6:54 a.m. UTC 
In RV32, we may have the need to read both low 32 bit and high 32 bit of
the CSR. Therefore adding the csr_read_hi_lo() and csr_write_hi_lo() to
support such case.

Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Suggested-by: Zong Li <zong.li@sifive.com>
Signed-off-by: Nick Hu <nick.hu@sifive.com>
---
 arch/riscv/include/asm/csr.h | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
diff mbox series

Patch

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 25966995da04..54198284eb22 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -501,6 +501,17 @@ 
 	__v;							\
 })
 
+#if __riscv_xlen < 64
+#define csr_read_hi_lo(csr)					\
+({								\
+	u32 hi = csr_read(csr##H);				\
+	u32 lo = csr_read(csr);					\
+	lo | ((u64)hi << 32);					\
+})
+#else
+#define csr_read_hi_lo	csr_read
+#endif
+
 #define csr_write(csr, val)					\
 ({								\
 	unsigned long __v = (unsigned long)(val);		\
@@ -509,6 +520,17 @@ 
 			      : "memory");			\
 })
 
+#if __riscv_xlen < 64
+#define csr_write_hi_lo(csr, val)				\
+({								\
+	u64 _v = (u64)(val);					\
+	csr_write(csr##H, (_v) >> 32);				\
+	csr_write(csr, (_v));					\
+})
+#else
+#define csr_write_hi_lo	csr_write
+#endif
+
 #define csr_read_set(csr, val)					\
 ({								\
 	unsigned long __v = (unsigned long)(val);		\