@@ -313,10 +313,9 @@ static const struct soc_device_attribute k3_cpufreq_soc[] = {
static struct ti_cpufreq_soc_data am625_soc_data = {
.efuse_xlate = am625_efuse_xlate,
- .efuse_offset = 0x0018,
+ .efuse_offset = 0x0,
.efuse_mask = 0x07c0,
.efuse_shift = 0x6,
- .rev_offset = 0x0014,
.multi_regulator = false,
};
@@ -325,7 +324,6 @@ static struct ti_cpufreq_soc_data am62a7_soc_data = {
.efuse_offset = 0x0,
.efuse_mask = 0x07c0,
.efuse_shift = 0x6,
- .rev_offset = 0x0014,
.multi_regulator = false,
};
@@ -334,7 +332,6 @@ static struct ti_cpufreq_soc_data am62p5_soc_data = {
.efuse_offset = 0x0,
.efuse_mask = 0x07c0,
.efuse_shift = 0x6,
- .rev_offset = 0x0014,
.multi_regulator = false,
};
@@ -349,11 +346,26 @@ static int ti_cpufreq_get_efuse(struct ti_cpufreq_data *opp_data,
u32 *efuse_value)
{
struct device *dev = opp_data->cpu_dev;
+ struct device_node *np = of_find_node_by_path("/bus@f0000/bus@b00000/syscon@43000000");
u32 efuse;
int ret;
- ret = regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset,
- &efuse);
+ /*
+ * This checks for old AM625 Devicetrees where the syscon was a phandle to the
+ * wkup_conf parent, this required a hard-coded offset to the efuse register.
+ * This node had the compatibles "syscon", "simple-mfd".
+ */
+ if (of_device_is_compatible(np, "simple-mfd") &&
+ of_machine_is_compatible("ti,am625")) {
+ dev_warn(dev,
+ "%s: An old devicetree is in use, please consider updating at some point!",
+ __func__);
+ ret = regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset + 0x0018,
+ &efuse);
+ } else {
+ ret = regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset,
+ &efuse);
+ }
if (opp_data->soc_data->quirks & TI_QUIRK_SYSCON_MAY_BE_MISSING && ret == -EIO) {
/* not a syscon register! */
void __iomem *regs = ioremap(OMAP3_SYSCON_BASE +
With the Silicon revision being taken directly from socinfo, there's no longer any need for reading any SOC register for revision from this driver. Hence, we do not require any rev_offset for AM62 family of devices. The efuse offset should be 0x0 for AM625 as well, as the syscon register being used from DT refers to the efuse_offset directly. However, to maintain the backward compatibility with old devicetree, also add condition to handle the case where we have the wrong offset and add the older efuse_offset value there such that we don't end up reading the wrong register offset. Signed-off-by: Dhruva Gole <d-gole@ti.com> --- drivers/cpufreq/ti-cpufreq.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-)