From patchwork Wed Sep 25 14:54:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruva Gole X-Patchwork-Id: 831473 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01464188903; Wed, 25 Sep 2024 14:55:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727276107; cv=none; b=CugcR9fPYHZ4HLxRzCPB9Ihz3T42PyPHEEYF56E2eCIbZt06P81Td7mHbi7Xm0QLEwc9q0TIF0vIQ8kw+5YyPUa81JB7G4kYJv3+SrQx31t6AtdgCQl0IbyQaeaBloTsmIANmi04u+mO4o/yPxp+cyWlJS75y5KnwIpzr6BHIqY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727276107; c=relaxed/simple; bh=gmxyRsRvrN/GW7kRQnE8u/bLH36aFbd2B6dpmrkb7U4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=cxSmU9tcWNGd5zLOrDyeYiMFyMKlSrc6vTD4TfIEPFie/r9kBjc5qsVJMFPKPcPxPW59lXuWuSd7d70Mcfqh4cmCEfnIF6SYKO4y2/63qGsohs/1bUoNdIc3ATaxEKz6uk2lSJSpzqR0M64zOKiPvBQmxUBIDRDBZ1kBiS8/o7g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=bEdQdSYQ; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="bEdQdSYQ" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 48PEt04b019912; Wed, 25 Sep 2024 09:55:00 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1727276100; bh=zLhShaVN27E261VkbondnBJqweCJB7QrnU+MuM8Qq0E=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=bEdQdSYQSmod1tr4TH/FieCAdOVIDlZLq7bdimmysaTSctFtmecjo1zHnXKc9FcvS irYtSuC9riarZKaoNXEwRiF1j7D3Lenmkhg9aLukmdbCHMNRF+c8k8XUgSpwqll78A IDg/oXw65kBM4p041Lxhe1Yh7zhcL/+yxRtfAcBI= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 48PEt0Gh101484 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 25 Sep 2024 09:55:00 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 25 Sep 2024 09:55:00 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 25 Sep 2024 09:55:00 -0500 Received: from [127.0.1.1] (lcpd911.dhcp.ti.com [172.24.227.226]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 48PEsYCm110564; Wed, 25 Sep 2024 09:54:56 -0500 From: Dhruva Gole Date: Wed, 25 Sep 2024 20:24:19 +0530 Subject: [PATCH v6 5/6] arm64: dts: ti: k3-am62: use opp_efuse_table for opp-table syscon Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240925-ti-cpufreq-fixes-v5-v6-5-46f41a903e01@ti.com> References: <20240925-ti-cpufreq-fixes-v5-v6-0-46f41a903e01@ti.com> In-Reply-To: <20240925-ti-cpufreq-fixes-v5-v6-0-46f41a903e01@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar CC: , , , , Andrew Davis , Bryan Brattlof , Dhruva Gole X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727276075; l=2062; i=d-gole@ti.com; s=20240919; h=from:subject:message-id; bh=gmxyRsRvrN/GW7kRQnE8u/bLH36aFbd2B6dpmrkb7U4=; b=87TQHfsigrFfETDy4MqE4neoK+ZwlIhOIs4Bir7A21iSSdRZHCvrRIklJJH880ajHN1oFToft 9shylYjNDXZCGuRJnDWb4HTw/9ZhoyKXOxieL/YhUrlxvTm3bD5lWIe X-Developer-Key: i=d-gole@ti.com; a=ed25519; pk=k8NnY4RbxVqeqGsYfTHeVn4hPOHkjg7Mii0Ixs4rghM= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Add another entry in the wkup_conf for the syscon node, and then use that for the syscon in opp-table. Marking entire wkup_conf as "syscon", "simple-mfd" is wrong and needs to be addressed similar to how other child-nodes in wkup_conf are implemented in the same file. Also, rename syscon to bus and drop reg = <>; Signed-off-by: Dhruva Gole --- arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 10 +++++++--- arch/arm64/boot/dts/ti/k3-am625.dtsi | 2 +- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi index e0afafd532a5c63f29ca0dabc541ffa22dde609b..9933bb55b00532fbd5ea74fc90036ab0eadd50bc 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -8,10 +8,9 @@ #include &cbass_wakeup { - wkup_conf: syscon@43000000 { + wkup_conf: bus@43000000 { bootph-all; - compatible = "syscon", "simple-mfd"; - reg = <0x00 0x43000000 0x00 0x20000>; + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x00 0x43000000 0x20000>; @@ -22,6 +21,11 @@ chipid: chipid@14 { reg = <0x14 0x4>; }; + opp_efuse_table: syscon@18 { + compatible = "ti,am62-opp-efuse-table", "syscon"; + reg = <0x18 0x4>; + }; + cpsw_mac_syscon: ethernet-mac-syscon@200 { compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; reg = <0x200 0x8>; diff --git a/arch/arm64/boot/dts/ti/k3-am625.dtsi b/arch/arm64/boot/dts/ti/k3-am625.dtsi index c3d1db47dc9f351d217721c0b9e46a0c68995838..c249883a8a8d846aa21092c4c341fd443cfcec15 100644 --- a/arch/arm64/boot/dts/ti/k3-am625.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am625.dtsi @@ -108,7 +108,7 @@ cpu3: cpu@3 { a53_opp_table: opp-table { compatible = "operating-points-v2-ti-cpu"; opp-shared; - syscon = <&wkup_conf>; + syscon = <&opp_efuse_table>; opp-200000000 { opp-hz = /bits/ 64 <200000000>;