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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a868f484dc5sm134189166b.171.2024.08.22.08.28.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2024 08:28:21 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, mturquette@baylibre.com, sboyd@kernel.org, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com, ulf.hansson@linaro.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 03/16] dt-bindings: reset: renesas,r9a08g045-sysc: Add reset IDs for RZ/G3S SYSC reset Date: Thu, 22 Aug 2024 18:27:48 +0300 Message-Id: <20240822152801.602318-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> References: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add reset IDs for the Renesas RZ/G3S SYSC reset controller driver. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- include/dt-bindings/reset/renesas,r9a08g045-sysc.h | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 include/dt-bindings/reset/renesas,r9a08g045-sysc.h diff --git a/include/dt-bindings/reset/renesas,r9a08g045-sysc.h b/include/dt-bindings/reset/renesas,r9a08g045-sysc.h new file mode 100644 index 000000000000..675872a32121 --- /dev/null +++ b/include/dt-bindings/reset/renesas,r9a08g045-sysc.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef __DT_BINDINGS_RESET_R9A08G045_SYSC_H +#define __DT_BINDINGS_RESET_R9A08G045_SYSC_H + +#define R9A08G045_SYSC_RESET_USB 0 +#define R9A08G045_SYSC_RESET_PCIE 1 + +#endif /* __DT_BINDINGS_RESET_SAMA7G5_H */ +