[16/16] arm64: defconfig: Enable RZ/G3S SYSC reset driver

Message ID	20240822152801.602318-17-claudiu.beznea.uj@bp.renesas.com
State	New
Headers	show Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D27C1D1F47 for <linux-pm@vger.kernel.org>; Thu, 22 Aug 2024 15:28:51 +0000 (UTC) From: Claudiu <claudiu.beznea@tuxon.dev> To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, mturquette@baylibre.com, sboyd@kernel.org, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com, ulf.hansson@linaro.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Subject: [PATCH 16/16] arm64: defconfig: Enable RZ/G3S SYSC reset driver Date: Thu, 22 Aug 2024 18:28:01 +0300 Message-Id: <20240822152801.602318-17-claudiu.beznea.uj@bp.renesas.com> In-Reply-To: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> References: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	Add initial USB support for the Renesas RZ/G3S SoC \| expand [00/16] Add initial USB support for the Renesas RZ/G3S SoC [01/16] clk: renesas: r9a08g045: Add clocks, resets and power domains for USB [02/16] dt-bindings: soc: renesas: renesas,rzg2l-sysc: Add #reset-cells for RZ/G3S [03/16] dt-bindings: reset: renesas,r9a08g045-sysc: Add reset IDs for RZ/G3S SYSC reset [05/16] soc: renesas: sysc: Move RZ/G3S SoC detection on SYSC driver [06/16] dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S SoC [07/16] reset: rzg2l-usbphy-ctrl: Get reset control array [08/16] reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S [09/16] dt-bindings: usb: renesas,usbhs: Document RZ/G3S SoC [10/16] phy: renesas: rcar-gen3-usb2: Add support to initialize the bus [11/16] dt-bindings: phy: renesas,usb2-phy: Document RZ/G3S phy bindings [12/16] phy: renesas: rcar-gen3-usb2: Add support for the RZ/G3S SoC [13/16] arm64: dts: renesas: Add #reset-cells to system controller node [14/16] arm64: dts: renesas: r9a08g045: Add USB support [15/16] arm64: dts: renesas: rzg3s-smarc: Enable USB support [16/16] arm64: defconfig: Enable RZ/G3S SYSC reset driver

Message ID

20240822152801.602318-17-claudiu.beznea.uj@bp.renesas.com

State

New

Headers

From: Claudiu <claudiu.beznea@tuxon.dev>
To: vkoul@kernel.org,
	kishon@kernel.org,
	robh@kernel.org,
	krzk+dt@kernel.org,
	conor+dt@kernel.org,
	p.zabel@pengutronix.de,
	geert+renesas@glider.be,
	magnus.damm@gmail.com,
	gregkh@linuxfoundation.org,
	mturquette@baylibre.com,
	sboyd@kernel.org,
	yoshihiro.shimoda.uh@renesas.com,
	biju.das.jz@bp.renesas.com,
	ulf.hansson@linaro.org
Cc: linux-phy@lists.infradead.org,
	devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-renesas-soc@vger.kernel.org,
	linux-usb@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-clk@vger.kernel.org,
	linux-pm@vger.kernel.org,
	claudiu.beznea@tuxon.dev,
	Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Subject: [PATCH 16/16] arm64: defconfig: Enable RZ/G3S SYSC reset driver
Date: Thu, 22 Aug 2024 18:28:01 +0300
Message-Id: <20240822152801.602318-17-claudiu.beznea.uj@bp.renesas.com>
In-Reply-To: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com>
References: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com>
Precedence: bulk
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit

Series

Add initial USB support for the Renesas RZ/G3S SoC | expand

Commit Message

Claudiu Beznea Aug. 22, 2024, 3:28 p.m. UTC

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Enable RZ/G3S SYSC reset driver. This exports the control to 2 signals
(one for USB, one for PCI).

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 7d32fca64996..4720367a41ea 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1510,6 +1510,7 @@  CONFIG_RESET_IMX7=y
 CONFIG_RESET_QCOM_AOSS=y
 CONFIG_RESET_QCOM_PDC=m
 CONFIG_RESET_RZG2L_USBPHY_CTRL=y
+CONFIG_RESET_RZG3S_SYSC=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_PHY_XGENE=y
 CONFIG_PHY_CAN_TRANSCEIVER=m

[16/16] arm64: defconfig: Enable RZ/G3S SYSC reset driver

Commit Message

Patch