diff mbox series

[6/9] arm64: dts: mediatek: mt8186: add default thermal zones

Message ID 20240111223020.3593558-7-nico@fluxnic.net
State Superseded
Headers show
Series Mediatek thermal sensor driver support for MT8186 and MT8188 | expand

Commit Message

Nicolas Pitre Jan. 11, 2024, 10:30 p.m. UTC 
From: Nicolas Pitre <npitre@baylibre.com>

Inspired by the vendor kernel but adapted to the upstream thermal
driver version.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
---
 arch/arm64/boot/dts/mediatek/mt8186.dtsi | 236 +++++++++++++++++++++++
 1 file changed, 236 insertions(+)

Comments

Krzysztof Kozlowski Jan. 12, 2024, 11:21 a.m. UTC | #1 
On 11/01/2024 23:30, Nicolas Pitre wrote:
> From: Nicolas Pitre <npitre@baylibre.com>
> 
> Inspired by the vendor kernel but adapted to the upstream thermal
> driver version.

DTS should not go via PM tree, so you need to Cc Mediatek SoC
maintainers. b4 would do this automatically. Other way is using
get_maintainers.pl.


> 
> Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8186.dtsi | 236 +++++++++++++++++++++++
>  1 file changed, 236 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> index 8fc563dce6..91b902a9f0 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -13,6 +13,8 @@
>  #include <dt-bindings/power/mt8186-power.h>
>  #include <dt-bindings/phy/phy.h>
>  #include <dt-bindings/reset/mt8186-resets.h>
> +#include <dt-bindings/thermal/thermal.h>
> +#include <dt-bindings/thermal/mediatek,lvts-thermal.h>
>  
>  / {
>  	compatible = "mediatek,mt8186";
> @@ -2115,4 +2117,238 @@ larb19: smi@1c10f000 {
>  			power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
>  		};
>  	};
> +
> +	thermal_zones: thermal-zones {
> +		cpu_zone0-thermal {

No underscores in node names. Could one CPU have multiple names? If not,
then it is just "cpu0-thermal".

Best regards,
Krzysztof
Nicolas Pitre Jan. 12, 2024, 4:52 p.m. UTC | #2 
On Fri, 12 Jan 2024, Krzysztof Kozlowski wrote:

> On 11/01/2024 23:30, Nicolas Pitre wrote:
> > From: Nicolas Pitre <npitre@baylibre.com>
> > 
> > Inspired by the vendor kernel but adapted to the upstream thermal
> > driver version.
> 
> DTS should not go via PM tree, so you need to Cc Mediatek SoC
> maintainers. b4 would do this automatically. Other way is using
> get_maintainers.pl.

Sure. But I'd prefer to have reviews making sure those patches are sane 
enough before spamming more people with this.


Nicolas
Nicolas Pitre Jan. 15, 2024, 5:46 p.m. UTC | #3 
On Fri, 12 Jan 2024, Krzysztof Kozlowski wrote:

> On 11/01/2024 23:30, Nicolas Pitre wrote:
> 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > index 8fc563dce6..91b902a9f0 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > @@ -2115,4 +2117,238 @@ larb19: smi@1c10f000 {
> >  			power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
> >  		};
> >  	};
> > +
> > +	thermal_zones: thermal-zones {
> > +		cpu_zone0-thermal {
> 
> No underscores in node names. Could one CPU have multiple names? If not,
> then it is just "cpu0-thermal".

Well... I'm not completely clear about this given the available info, 
but this thermal zone would not be matching a single CPU but a few of 
them, hence several "zones of CPUs".


Nicolas
Krzysztof Kozlowski Jan. 15, 2024, 5:52 p.m. UTC | #4 
On 15/01/2024 18:46, Nicolas Pitre wrote:
>>> @@ -2115,4 +2117,238 @@ larb19: smi@1c10f000 {
>>>  			power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
>>>  		};
>>>  	};
>>> +
>>> +	thermal_zones: thermal-zones {
>>> +		cpu_zone0-thermal {
>>
>> No underscores in node names. Could one CPU have multiple names? If not,
>> then it is just "cpu0-thermal".
> 
> Well... I'm not completely clear about this given the available info, 
> but this thermal zone would not be matching a single CPU but a few of 
> them, hence several "zones of CPUs".

OK, then just: cpu-zone0-thermal

Best regards,
Krzysztof
Daniel Lezcano Jan. 19, 2024, 5:04 p.m. UTC | #5 
On 15/01/2024 18:52, Krzysztof Kozlowski wrote:
> On 15/01/2024 18:46, Nicolas Pitre wrote:
>>>> @@ -2115,4 +2117,238 @@ larb19: smi@1c10f000 {
>>>>   			power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
>>>>   		};
>>>>   	};
>>>> +
>>>> +	thermal_zones: thermal-zones {
>>>> +		cpu_zone0-thermal {
>>>
>>> No underscores in node names. Could one CPU have multiple names? If not,
>>> then it is just "cpu0-thermal".
>>
>> Well... I'm not completely clear about this given the available info,
>> but this thermal zone would not be matching a single CPU but a few of
>> them, hence several "zones of CPUs".
> 
> OK, then just: cpu-zone0-thermal

Given the node name is used as the thermal zone name. The 'zone' is 
duplicate in the namespace.

/sys/class/thermal/thermal_zone0/type = cpu-zone0-thermal

Furthermore, if other thermal zones are registered before, that could be:

/sys/class/thermal/thermal_zone4/type = cpu-zone0-thermal

Kind of inconsistent :/

If it is a group of CPUS, they are probably belonging to the same 
performance domain, may be we can use the name 'cluster' here:

	cluster0-thermal
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 8fc563dce6..91b902a9f0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -13,6 +13,8 @@ 
 #include <dt-bindings/power/mt8186-power.h>
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/reset/mt8186-resets.h>
+#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/thermal/mediatek,lvts-thermal.h>
 
 / {
 	compatible = "mediatek,mt8186";
@@ -2115,4 +2117,238 @@  larb19: smi@1c10f000 {
 			power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
 		};
 	};
+
+	thermal_zones: thermal-zones {
+		cpu_zone0-thermal {
+			polling-delay = <1000>;
+			polling-delay-passive = <250>;
+			thermal-sensors = <&lvts MT8186_TS1_0>;
+
+			trips {
+				cpu_zone0_alert: trip-alert {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu_zone0_crit: trip-crit {
+					temperature = <100000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_zone0_alert>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		cpu_zone1-thermal {
+			polling-delay = <1000>;
+			polling-delay-passive = <250>;
+			thermal-sensors = <&lvts MT8186_TS1_1>;
+
+			trips {
+				cpu_zone1_alert: trip-alert {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu_zone1_crit: trip-crit {
+					temperature = <100000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_zone1_alert>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		cpu_zone2-thermal {
+			polling-delay = <1000>;
+			polling-delay-passive = <250>;
+			thermal-sensors = <&lvts MT8186_TS1_2>;
+
+			trips {
+				cpu_zone2_alert: trip-alert {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu_zone2_crit: trip-crit {
+					temperature = <100000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_zone2_alert>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		cam-thermal {
+			polling-delay = <1000>;
+			polling-delay-passive = <250>;
+			thermal-sensors = <&lvts MT8186_TS1_3>;
+
+			trips {
+				cam_alert: trip-alert {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cam_crit: trip-crit {
+					temperature = <100000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		nna-thermal {
+			polling-delay = <1000>;
+			polling-delay-passive = <250>;
+			thermal-sensors = <&lvts MT8186_TS3_0>;
+
+			trips {
+				nna_alert: trip-alert {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				nna_crit: trip-crit {
+					temperature = <100000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		adsp-thermal {
+			polling-delay = <1000>;
+			polling-delay-passive = <250>;
+			thermal-sensors = <&lvts MT8186_TS3_1>;
+
+			trips {
+				adsp_alert: trip-alert {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				adsp_crit: trip-crit {
+					temperature = <100000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		mfg-thermal {
+			polling-delay = <1000>;
+			polling-delay-passive = <250>;
+			thermal-sensors = <&lvts MT8186_TS3_2>;
+
+			trips {
+				mfg_alert: trip-alert {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				mfg_crit: trip-crit {
+					temperature = <100000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu_big0-thermal {
+			polling-delay = <1000>;
+			polling-delay-passive = <250>;
+			thermal-sensors = <&lvts MT8186_TS2_0>;
+
+			trips {
+				cpu_big0_alert: trip-alert {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu_big0_crit: trip-crit {
+					temperature = <100000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_big0_alert>;
+					cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		cpu_big1-thermal {
+			polling-delay = <1000>;
+			polling-delay-passive = <250>;
+			thermal-sensors = <&lvts MT8186_TS2_1>;
+
+			trips {
+				cpu_big1_alert: trip-alert {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu_big1_crit: trip-crit {
+					temperature = <100000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_big1_alert>;
+					cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
 };