From patchwork Fri Sep 29 11:57:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 728475 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79593E810DF for ; Fri, 29 Sep 2023 11:57:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233117AbjI2L54 (ORCPT ); Fri, 29 Sep 2023 07:57:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45932 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233125AbjI2L5z (ORCPT ); Fri, 29 Sep 2023 07:57:55 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0171ECC0; Fri, 29 Sep 2023 04:57:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695988673; x=1727524673; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hHkykAT64KFeDdyczTYQ6xW3x+LfVkMtEWBZ1a9eYwk=; b=SeAWNw5+JpwyjyMMRUADm82ZBBoH2lA9EMGM/9NlRGC3CkW0pGsTHwxU WJcbtqUl/PTJfzXiOTMyhRzz+ElAsizJ3yWD+u/gVhY6GRVml3WFrzzQy oXOtAV4zXLKxXscmJlX3kbWlqqiaXVS/dMKWukppNBxEKYIWrQzUkpjpf u+NSxnl/VLFBUC87Eb2uRAGaA0qB/UVWlNx48ttCEOG8i07gObNZDeFMy xeATnAZpQkl9ogT9Wl8WSDJDOH8T/Yj9BZ+S+0aifd3GaAHIqpoC1dxMs SnwpSdR2coeBHF2tGjC7lB8NROsU2IqZUmkE/V40z9xVy409KchVw7ZUR Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10847"; a="413185323" X-IronPort-AV: E=Sophos;i="6.03,187,1694761200"; d="scan'208";a="413185323" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Sep 2023 04:57:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,187,1694761200"; d="scan'208";a="838581" Received: from valeks2x-mobl.ger.corp.intel.com (HELO localhost) ([10.252.53.242]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Sep 2023 04:57:46 -0700 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Lukas Wunner , Alexandru Gagniuc , Krishna chaitanya chundru , Srinivas Pandruvada , "Rafael J . Wysocki" , linux-pm@vger.kernel.org, Bjorn Helgaas , Jonathan Corbet , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Alex Deucher , Daniel Lezcano , Amit Kucheria , Zhang Rui , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH v3 01/10] PCI: Protect Link Control 2 Register with RMW locking Date: Fri, 29 Sep 2023 14:57:14 +0300 Message-Id: <20230929115723.7864-2-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230929115723.7864-1-ilpo.jarvinen@linux.intel.com> References: <20230929115723.7864-1-ilpo.jarvinen@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org PCIe Bandwidth Controller performs RMW accesses the Link Control 2 Register which can occur concurrently to other sources of Link Control 2 Register writes. Therefore, add Link Control 2 Register among the PCI Express Capability Registers that need RMW locking. Signed-off-by: Ilpo Järvinen --- Documentation/PCI/pciebus-howto.rst | 8 ++++---- include/linux/pci.h | 1 + 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/Documentation/PCI/pciebus-howto.rst b/Documentation/PCI/pciebus-howto.rst index a0027e8fb0d0..3ba322ca1ce1 100644 --- a/Documentation/PCI/pciebus-howto.rst +++ b/Documentation/PCI/pciebus-howto.rst @@ -218,7 +218,7 @@ that is shared between many drivers including the service drivers. RMW Capability accessors (pcie_capability_clear_and_set_word(), pcie_capability_set_word(), and pcie_capability_clear_word()) protect a selected set of PCI Express Capability Registers (Link Control -Register and Root Control Register). Any change to those registers -should be performed using RMW accessors to avoid problems due to -concurrent updates. For the up-to-date list of protected registers, -see pcie_capability_clear_and_set_word(). +Register, Root Control Register, and Link Control 2 Register). Any +change to those registers should be performed using RMW accessors to +avoid problems due to concurrent updates. For the up-to-date list of +protected registers, see pcie_capability_clear_and_set_word(). diff --git a/include/linux/pci.h b/include/linux/pci.h index 8c7c2c3c6c65..16db80f8b15c 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1243,6 +1243,7 @@ static inline int pcie_capability_clear_and_set_word(struct pci_dev *dev, { switch (pos) { case PCI_EXP_LNKCTL: + case PCI_EXP_LNKCTL2: case PCI_EXP_RTCTL: return pcie_capability_clear_and_set_word_locked(dev, pos, clear, set);