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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id a9-20020a2eb549000000b00295735991edsm1261639ljn.38.2023.03.16.07.13.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Mar 2023 07:13:14 -0700 (PDT) From: Konrad Dybcio Date: Thu, 16 Mar 2023 15:12:58 +0100 Subject: [PATCH v2 09/14] arm64: dts: qcom: sm6375: Add CPUCP L3 node MIME-Version: 1.0 Message-Id: <20230303-topic-sm6375_features0_dts-v2-9-708b8191f7eb@linaro.org> References: <20230303-topic-sm6375_features0_dts-v2-0-708b8191f7eb@linaro.org> In-Reply-To: <20230303-topic-sm6375_features0_dts-v2-0-708b8191f7eb@linaro.org> To: Amit Kucheria , Thara Gopinath , Andy Gross , Bjorn Andersson , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Rob Herring , Krzysztof Kozlowski , Georgi Djakov , Sibi Sankar Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678975978; l=1031; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=qJFA3gnp5+qsVvXTr+LuzoDVV2GfdNaVud8C8hVxcw8=; b=CEOtCUVU+F/M8OU5WvP/wsLQQcbZu4R5ctBaSEtpjhEkXFNGQRxIAbLXaHDWexBuec8kzWqg61sL 3DeLprBOCzTdwE3eoq/GrrqgewOHfGjuBR3A+45KcdCSsoQ4NE1T X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Configure the L3 cache DVFS scaler within the CPUCP block to allow for dynamic frequency switching. Reviewed-by: Sibi Sankar Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 90f18754a63b..59d7ed25aa36 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -1505,6 +1505,15 @@ frame@f42d000 { }; }; + cpucp_l3: interconnect@fd90000 { + compatible = "qcom,sm6375-cpucp-l3", "qcom,epss-l3"; + reg = <0 0x0fd90000 0 0x1000>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@fd91000 { compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss"; reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>;