From patchwork Thu Jan 19 11:50:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wyes Karny X-Patchwork-Id: 644529 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D5EBC46467 for ; Thu, 19 Jan 2023 11:52:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230169AbjASLwB (ORCPT ); Thu, 19 Jan 2023 06:52:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230235AbjASLwA (ORCPT ); Thu, 19 Jan 2023 06:52:00 -0500 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2043.outbound.protection.outlook.com [40.107.223.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED693302AA; Thu, 19 Jan 2023 03:51:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=LD/ib+pei047tkZsycf7B0nSRddMsdTRS4eGYilD70idZDvn5dikiK5nafUGdI3MlemqZAFrJyoL3T4hsvmspFAhobvt+iI0VsfblIqmI3hp93y2zfrDGq83NBgarCGd6c3jeo5r2BQLHtPJlBbF/wqWY0+XjNRQ+n3zu0bzqJFXIXM8/GwtgKUroTrQnC00sONQj2MKPuroedVb1+IJot/1BnbGT3CaXEL9BMLvkWwt9FAS6jd2rCAZ0SF90jvSsIjFNbdp8Z/LMU4dzZkoG6MIrNAgq6w76uR4UKheYipCiFDm6j23cNFr1iJQJY1wbtOUcOQYERaDOaicJ7VZXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=bhVkymXeHoZowm758idB9fs3vqfG/nYfIbxZHkSfneI=; b=Gk89lK4iRvX7cYHSDXJ+tGyEsFKIP/kQKY2jRIZcwRKSNX54D70Pt3Yp25gYOFjHPtWLXi1hXubmTYXFm6aiaMzKr+fHjIRqJQGKTPLSLBFPhsf6vd+VoMMbF2RtqFaiS6KZca0jvFeAXuc32xyg+VSxPoDjMno3LoCpPSEcJe8r9vnaOg2jZaqnXs23EgFBgXgmmPDNVMhVgJmZ0pPHyK28Y96R+TYtdwoIAqplR+nQhR5Ks2i+LLVA2ML1YQmtOxupH+lGt/LahIGBhPe9HgPVB5wiQh7cs2PB965Wqdhsi/Y8u4cdG5r7U7OiHYApOHu4wPnUCnsFWey2Cmhw4Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bhVkymXeHoZowm758idB9fs3vqfG/nYfIbxZHkSfneI=; b=4Z2Mp+x7jY2C9rrDk449WSp/ZK+BN9LqnrFATbzJv1soG0qOu6IdunK/4ieABPM24AlWu7BVGeY42jLpKy1ZYpIKyXO3yHRJvf7QVMm+/HhDQFXeguuv/DPSwrxxWukVLEIJmLoLGRBXzIIh9IOlOPRioB5BcLJ1XEJTYjOyb+E= Received: from DM6PR03CA0032.namprd03.prod.outlook.com (2603:10b6:5:40::45) by BL1PR12MB5349.namprd12.prod.outlook.com (2603:10b6:208:31f::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.13; Thu, 19 Jan 2023 11:51:57 +0000 Received: from DM6NAM11FT028.eop-nam11.prod.protection.outlook.com (2603:10b6:5:40:cafe::f0) by DM6PR03CA0032.outlook.office365.com (2603:10b6:5:40::45) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.25 via Frontend Transport; Thu, 19 Jan 2023 11:51:57 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT028.mail.protection.outlook.com (10.13.173.140) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6023.16 via Frontend Transport; Thu, 19 Jan 2023 11:51:56 +0000 Received: from beas.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 19 Jan 2023 05:51:51 -0600 From: Wyes Karny To: Rafael J Wysocki , Huang Rui , Jonathan Corbet , Viresh Kumar , , , Ananth Narayan , CC: , , , Bagas Sanjaya , , Len Brown , Robert Moore , Borislav Petkov , Wyes Karny , Mario Limonciello Subject: [PATCH v3 2/6] acpi: cppc: Add auto select register read/write support Date: Thu, 19 Jan 2023 11:50:13 +0000 Message-ID: <20230119115017.10188-3-wyes.karny@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230119115017.10188-1-wyes.karny@amd.com> References: <20230119115017.10188-1-wyes.karny@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT028:EE_|BL1PR12MB5349:EE_ X-MS-Office365-Filtering-Correlation-Id: 2a63b335-fea0-46d1-1589-08dafa1390f1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: MRvvuNDNxlMOhSIGXfWvoGdOVnNNButv70DzHhnvbQYmb4yuYa75VoHwQsThck8ufBN+SbNRSXWtEEkilUkusg810zYhEgXR4hhI2XX5x8vCFj1PDfdXoydVdip4Gx1lOX+LQaLfuGs+5xnCt+DhVxN3rMRWNX/p5ZkXXBiDmR0R2odCLIYy8BbQQ4dS7zUHkLjJ3IUImaKFlxfpRsp/AQZt1wThDhgrjmXOLlCrSh5HK/ffF30zybb7yhJ864gEL0uPwgEOARaabInY933m0k0y9t+uV002+DWPADiPUyYN8szj643Nst3B6nUeRKhvsRs8A3FGx51IycT2yH4z/0RLBPVNB44dqU1lmvo6BhBeJ5gLboOOiPnshTEq1FQru0y0fMGAY0ZAFKdikBGcYQ72bN0R4HPxwoY1Jq1WDautNefyS8/0IwotHCyGPD+HpXphIrLhoLtWr6P3eMtHASYpTS78x+lHD7D3xgU5RtXkOX2dqePU7ZH6RjlQJNXVLkxJMKzXlfutfWAjJN84tE8/bB8ghFayUYGESes1YmjJCcFRCPo1i40C4IzP2X0Lw0GrMOq6fCtFiuZZ8dWpncnQd32mFrK5DSkHz7KgMDzeKGXC59AIsa/y8UY17b4l4Zl4gmm99Rs4Sj30rh9/9k9XRyabUUDX4FzCQ8VgcaZwigVeJIdzkkWVynJHW+O6tk2jeYdU9e/Xcibh+6rhbRLtleMxQuHu0d3k65jm5OQ= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(346002)(39860400002)(396003)(376002)(136003)(451199015)(40470700004)(36840700001)(46966006)(8676002)(4326008)(70206006)(41300700001)(8936002)(110136005)(6666004)(44832011)(82740400003)(2616005)(82310400005)(316002)(6636002)(54906003)(2906002)(70586007)(1076003)(16526019)(40460700003)(36756003)(5660300002)(7416002)(86362001)(478600001)(7696005)(40480700001)(186003)(81166007)(36860700001)(26005)(356005)(83380400001)(336012)(426003)(47076005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2023 11:51:56.8606 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2a63b335-fea0-46d1-1589-08dafa1390f1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5349 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org For some AMD shared memory based systems, the autonomous selection bit needed to be set explicitly. Add autonomous selection register related APIs to acpi driver, which amd_pstate driver uses later. Signed-off-by: Wyes Karny Reviewed-by: Mario Limonciello --- drivers/acpi/cppc_acpi.c | 97 ++++++++++++++++++++++++++++++++++++++++ include/acpi/cppc_acpi.h | 11 +++++ 2 files changed, 108 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index c936ff503965..e47b2cfe022e 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1432,6 +1432,103 @@ int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable) } EXPORT_SYMBOL_GPL(cppc_set_epp_perf); +/* + * cppc_get_auto_sel_caps - Read autonomous selection register. + * @cpunum : CPU from which to read register. + * @perf_caps : struct where autonomous selection register value is updated. + */ +int cppc_get_auto_sel_caps(int cpunum, struct cppc_perf_caps *perf_caps) +{ + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); + struct cpc_register_resource *auto_sel_reg; + u64 auto_sel; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU:%d\n", cpunum); + return -ENODEV; + } + + auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; + + if (!CPC_SUPPORTED(auto_sel_reg)) + pr_warn_once("Autonomous mode is not unsupported!\n"); + + if (CPC_IN_PCC(auto_sel_reg)) { + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = 0; + + if (pcc_ss_id < 0) + return -ENODEV; + + pcc_ss_data = pcc_data[pcc_ss_id]; + + down_write(&pcc_ss_data->pcc_lock); + + if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) { + cpc_read(cpunum, auto_sel_reg, &auto_sel); + perf_caps->auto_sel = (bool)auto_sel; + } else { + ret = -EIO; + } + + up_write(&pcc_ss_data->pcc_lock); + + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(cppc_get_auto_sel_caps); + +/* + * cppc_set_auto_sel - Write autonomous selection register. + * @cpunum : CPU to which to write register. + * @enable : the desired value of autonomous selection resiter to be updated. + */ +int cppc_set_auto_sel(int cpu, bool enable) +{ + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); + struct cpc_register_resource *auto_sel_reg; + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = -EINVAL; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU:%d\n", cpu); + return -ENODEV; + } + + auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; + + if (CPC_IN_PCC(auto_sel_reg)) { + if (pcc_ss_id < 0) { + pr_debug("Invalid pcc_ss_id\n"); + return -ENODEV; + } + + if (CPC_SUPPORTED(auto_sel_reg)) { + ret = cpc_write(cpu, auto_sel_reg, enable); + if (ret) + return ret; + } + + pcc_ss_data = pcc_data[pcc_ss_id]; + + down_write(&pcc_ss_data->pcc_lock); + /* after writing CPC, transfer the ownership of PCC to platform */ + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE); + up_write(&pcc_ss_data->pcc_lock); + } else { + ret = -ENOTSUPP; + pr_debug("_CPC in PCC is not supported\n"); + } + + return ret; +} +EXPORT_SYMBOL_GPL(cppc_set_auto_sel); + + /** * cppc_set_enable - Set to enable CPPC on the processor by writing the * Continuous Performance Control package EnableRegister field. diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 6b487a5bd638..6126c977ece0 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -109,6 +109,7 @@ struct cppc_perf_caps { u32 lowest_freq; u32 nominal_freq; u32 energy_perf; + bool auto_sel; }; struct cppc_perf_ctrls { @@ -153,6 +154,8 @@ extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val); extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val); extern int cppc_get_epp_perf(int cpunum, u64 *epp_perf); extern int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable); +extern int cppc_get_auto_sel_caps(int cpunum, struct cppc_perf_caps *perf_caps); +extern int cppc_set_auto_sel(int cpu, bool enable); #else /* !CONFIG_ACPI_CPPC_LIB */ static inline int cppc_get_desired_perf(int cpunum, u64 *desired_perf) { @@ -214,6 +217,14 @@ static inline int cppc_get_epp_perf(int cpunum, u64 *epp_perf) { return -ENOTSUPP; } +static inline int cppc_set_auto_sel(int cpu, bool enable) +{ + return -ENOTSUPP; +} +static inline int cppc_get_auto_sel_caps(int cpunum, struct cppc_perf_caps *perf_caps) +{ + return -ENOTSUPP; +} #endif /* !CONFIG_ACPI_CPPC_LIB */ #endif /* _CPPC_ACPI_H*/