From patchwork Tue Nov 1 17:10:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vibhore Vardhan X-Patchwork-Id: 620777 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5DC2C4167B for ; Tue, 1 Nov 2022 17:10:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230348AbiKARKq (ORCPT ); Tue, 1 Nov 2022 13:10:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230245AbiKARKo (ORCPT ); Tue, 1 Nov 2022 13:10:44 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9EC8811A33; Tue, 1 Nov 2022 10:10:39 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2A1HAMcD055317; Tue, 1 Nov 2022 12:10:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1667322622; bh=NPJI/Nnc1LZFghCEy+uPvP0cfM7Z2t1AXwLTXXwiAdg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=V1tC9AIW6TNHzqwR3IEgulb8M2AVVNGOglJ1F3wWn344QnhO3FAyqnDYvMv6ip6ib VqCeskVRaxHn7Zly6mkSDMHhBKutn+jHV4BuFoeZs2CkUA2iSde+lKHr9GPw/VTUhi a49pw6iQ9GM6Xq7YRRUvUVnuOOAnptl3vgAIVJ1A= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2A1HAM7r087427 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 1 Nov 2022 12:10:22 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 1 Nov 2022 12:10:22 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 1 Nov 2022 12:10:22 -0500 Received: from maitri.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A1HAMwD106008; Tue, 1 Nov 2022 12:10:22 -0500 From: Vibhore Vardhan To: , , , , , , CC: , , , Subject: [3/5] arm64: dts: ti: k3-am625: Introduce operating-points table Date: Tue, 1 Nov 2022 12:10:20 -0500 Message-ID: <20221101171022.133322-4-vibhore@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221101171022.133322-1-vibhore@ti.com> References: <20221101171022.133322-1-vibhore@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Dave Gerlach Introduce an operating-points table for the A53 cores, containing only frequency values as this platform operates on a fixed voltage for the CPUs. Also provide opp-supported-hw values to ensure appropriate OPPs are enabled based on which type of silicon is in use. The latency between pre and post frequency transition was measured in CPUFreq driver for all combinations of OPP changes. The average value was selected as overall clock-latency-ns. Signed-off-by: Dave Gerlach Signed-off-by: Vibhore Vardhan --- arch/arm64/boot/dts/ti/k3-am625.dtsi | 51 ++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am625.dtsi b/arch/arm64/boot/dts/ti/k3-am625.dtsi index 887f31c23fef..911a0006ec00 100644 --- a/arch/arm64/boot/dts/ti/k3-am625.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am625.dtsi @@ -48,6 +48,8 @@ cpu0: cpu@0 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 135 0>; }; cpu1: cpu@1 { @@ -62,6 +64,8 @@ cpu1: cpu@1 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 136 0>; }; cpu2: cpu@2 { @@ -76,6 +80,8 @@ cpu2: cpu@2 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 137 0>; }; cpu3: cpu@3 { @@ -90,6 +96,51 @@ cpu3: cpu@3 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 138 0>; + }; + }; + + a53_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + opp-shared; + syscon = <&wkup_conf>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-supported-hw = <0x01 0x0006>; + clock-latency-ns = <6000000>; + }; + + opp-1250000000 { + opp-hz = /bits/ 64 <1250000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + opp-suspend; }; };