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[109.15.145.210]) by smtp.googlemail.com with ESMTPSA id u3-20020a5d4683000000b00225239d9265sm242056wrq.74.2022.09.20.08.03.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Sep 2022 08:03:51 -0700 (PDT) From: Amjad Ouled-Ameur Date: Tue, 20 Sep 2022 17:03:49 +0200 Subject: [PATCH v5 2/4] thermal: mediatek: control buffer enablement tweaks MIME-Version: 1.0 Message-Id: <20220920-i350-thermal-up-v5-2-123bc852d199@baylibre.com> References: <20220920-i350-thermal-up-v5-0-123bc852d199@baylibre.com> In-Reply-To: <20220920-i350-thermal-up-v5-0-123bc852d199@baylibre.com> To: Amit Kucheria , Rob Herring , Zhang Rui , Daniel Lezcano , "Rafael J. Wysocki" , Krzysztof Kozlowski Cc: Fabien Parent , Hsin-Yi Wang , Markus Schneider-Pargmann , linux-pm@vger.kernel.org, AngeloGioacchino Del Regno , Matthias Brugger , Michael Kao , Amjad Ouled-Ameur , Rob Herring , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.10.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1663686228; l=2347; i=aouledameur@baylibre.com; s=20220920; h=from:subject:message-id; bh=5q/fW4mpAQQZom7YMno2r4M6vJl67k0unrSVbaUfEJ8=; b=XlVTEXZVb137T29c44XMQm5WKed4jWjkqD0vT/9S8XW0ASP1lOEMbQT3VbT6aqgiabILmrb4jfbe PuxqMiI2Dm2YL6lh8uL1289P7KUrvFJ/Gw6bDdoCvJikuGYoVNVy X-Developer-Key: i=aouledameur@baylibre.com; a=ed25519; pk=HgYWawSL4qLGPx+RzJ+Cuu+V8Pi/KQnDDm1wjWPMOFE= Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Markus Schneider-Pargmann Add logic in order to be able to turn on the control buffer on MT8365. This change now allows to have control buffer support for MTK_THERMAL_V1, and it allows to define the register offset, and mask used to enable it. Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Fabien Parent Signed-off-by: Amjad Ouled-Ameur Reviewed-by: AngeloGioacchino Del Regno diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c index 8440692e3890..d8ddceb75372 100644 --- a/drivers/thermal/mtk_thermal.c +++ b/drivers/thermal/mtk_thermal.c @@ -271,6 +271,9 @@ struct mtk_thermal_data { bool need_switch_bank; struct thermal_bank_cfg bank_data[MAX_NUM_ZONES]; enum mtk_thermal_version version; + u32 apmixed_buffer_ctl_reg; + u32 apmixed_buffer_ctl_mask; + u32 apmixed_buffer_ctl_set; }; struct mtk_thermal { @@ -514,6 +517,9 @@ static const struct mtk_thermal_data mt7622_thermal_data = { .adcpnp = mt7622_adcpnp, .sensor_mux_values = mt7622_mux_values, .version = MTK_THERMAL_V2, + .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON1, + .apmixed_buffer_ctl_mask = GENMASK(31, 6) | BIT(3), + .apmixed_buffer_ctl_set = BIT(0), }; /* @@ -963,14 +969,18 @@ static const struct of_device_id mtk_thermal_of_match[] = { }; MODULE_DEVICE_TABLE(of, mtk_thermal_of_match); -static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base) +static void mtk_thermal_turn_on_buffer(struct mtk_thermal *mt, + void __iomem *apmixed_base) { - int tmp; + u32 tmp; + + if (!mt->conf->apmixed_buffer_ctl_reg) + return; - tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1); - tmp &= ~(0x37); - tmp |= 0x1; - writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1); + tmp = readl(apmixed_base + mt->conf->apmixed_buffer_ctl_reg); + tmp &= mt->conf->apmixed_buffer_ctl_mask; + tmp |= mt->conf->apmixed_buffer_ctl_set; + writel(tmp, apmixed_base + mt->conf->apmixed_buffer_ctl_reg); udelay(200); } @@ -1070,8 +1080,9 @@ static int mtk_thermal_probe(struct platform_device *pdev) goto err_disable_clk_auxadc; } + mtk_thermal_turn_on_buffer(mt, apmixed_base); + if (mt->conf->version == MTK_THERMAL_V2) { - mtk_thermal_turn_on_buffer(apmixed_base); mtk_thermal_release_periodic_ts(mt, auxadc_base); }