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SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230016)(4636009)(39860400002)(346002)(376002)(136003)(396003)(46966006)(40470700004)(36840700001)(81166007)(82310400005)(356005)(26005)(5660300002)(40460700003)(7696005)(478600001)(8936002)(86362001)(15650500001)(83380400001)(41300700001)(40480700001)(8676002)(2906002)(4326008)(316002)(82740400003)(36860700001)(110136005)(16526019)(426003)(54906003)(1076003)(2616005)(47076005)(186003)(36756003)(336012)(70586007)(70206006)(2101003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Aug 2022 16:39:20.7513 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 47ab9ae4-40c4-41fb-7ec5-08da7e1389d5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT040.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR1201MB0067 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Change the default transition latency to be 20ms that is more reasonable transition delay for AMD processors in non-EPP driver mode. Update transition delay time to 1ms, in the AMD CPU autonomous mode and non-autonomous mode, CPPC firmware will decide frequency at 1ms timescale based on the workload utilization. Acked-by: Viresh Kumar Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index e40177d14310..9cb051d61422 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -41,8 +41,8 @@ #include #include "amd-pstate-trace.h" -#define AMD_PSTATE_TRANSITION_LATENCY 0x20000 -#define AMD_PSTATE_TRANSITION_DELAY 500 +#define AMD_PSTATE_TRANSITION_LATENCY 20000 +#define AMD_PSTATE_TRANSITION_DELAY 1000 /* * TODO: We need more time to fine tune processors with shared memory solution