| Message ID | 20220709141927.836240-1-Perry.Yuan@amd.com |
|---|---|
| State | Superseded |
| Headers | show
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From: Perry Yuan <Perry.Yuan@amd.com>
To: <rafael.j.wysocki@intel.com>, <viresh.kumar@linaro.org>,
<Ray.Huang@amd.com>
CC: <Deepak.Sharma@amd.com>, <Mario.Limonciello@amd.com>,
<Nathan.Fontenot@amd.com>, <Alexander.Deucher@amd.com>,
<Jinzhou.Su@amd.com>, <Xinmei.Huang@amd.com>,
<Xiaojian.Du@amd.com>, <Li.Meng@amd.com>,
<linux-pm@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Perry Yuan <Perry.Yuan@amd.com>
Subject: [PATCH v2 09/14] cpufreq: amd-pstate: update pstate frequency
transition delay time
Date: Sat, 9 Jul 2022 10:19:27 -0400
Message-ID: <20220709141927.836240-1-Perry.Yuan@amd.com>
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| Series |
[v2,01/14] x86/msr: Add the MSR definition for AMD CPPC hardware control.
|
expand
|
diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index da20e17a140e..21037935e869 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -41,7 +41,7 @@ #include <asm/msr.h> #include "amd-pstate-trace.h" -#define AMD_PSTATE_TRANSITION_LATENCY 0x20000 +#define AMD_PSTATE_TRANSITION_LATENCY 20000 #define AMD_PSTATE_TRANSITION_DELAY 500 /*
change the default transition latency to be 20ms that is more reasonable transition delay for AMD processors in non-EPP driver mode. Signed-off-by: Perry Yuan <Perry.Yuan@amd.com> --- drivers/cpufreq/amd-pstate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)