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Peter Anvin" , Peter Zijlstra , Adrian Hunter , Pawan Gupta , Alexander Shishkin , Perry Yuan , "Chang S. Bae" , Huang Rui , Tony Luck , Ricardo Neri , CC: , , , , , , , , Subject: [PATCH 01/12] x86/msr: Add the MSR definition for AMD CPPC hardware control. Date: Thu, 7 Jul 2022 12:51:36 -0400 Message-ID: <20220707165137.211400-1-Perry.Yuan@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: aa90c8af-c751-48b2-a3d4-08da6039013b X-MS-TrafficTypeDiagnostic: BN6PR1201MB2482:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hmDu6B4aqLihL8HtdUZRsU4bJ9pNWPfxEkWH/XIAybSdW1V2i60WUAmdkJfJb7JDfIBXSMJx4w0MjnYl8Vl/ScUYeY+EWZBBHtYUA7Bv2u9cLOqTk97ydwOrkZwmyXSeiepSVjtTY52mvv4wOfDhhCtIBGbLu5+HFCBdR/U6kti6Z8fRmpKumcm7QPVfxMnrLrxzwo84AsAG/UuKdaMK2O4NTiRYBDDRFknZveaNn0rudk1a6ZvbWgDAEF4oJTiN2oaIwkMQC8ZiY6RW30Qkkivi8VDy2xtfK+UXU03se29A1kMcP+AWVl39oxFIqZf8qJllIICQ75LA/hVDyY8/Iz48/D/2/OZQiCxi91SCN/cv8rY3emQJddKWXEXXOc1vpHBWerlA79f1zN3RwMBZSgJkQrwVGBnwN3MzZlCWnX/uojAGRsPUlUA94inNmn9vtklXC3ObttL5uUw9DZMfBPn/rbacb+p4+FeQuaIP6+DiHyTxCzEYta/JZnLBzMoi/axeOp1C2PRAPmlmf0MghLKVTghL8W20qg6CkNtRHvSBFAhcl6sJwe0NVojNAJpa6Q4LhOWrNg27leaZlM4r/oxQGDRDAFNEeKhLwu8bJE7yxhVYOMOgm6O9k2KHei+mq1da5FxJYPdQXNK4tELkzWFlFeudJePJX7P3nRCn93WEqRXEhMp4/Wtk0HZCJwNzu+cQ2rXB9KnwtxMKNcORXi5+KM+1honSpv1q2/Zyzb9Q2ed6I922xq39q/peLnmQUTXGeL6MQGXsPL+ErhCvJPpLomUE//DL+zgR3r5cZYS3vVbzqTMzYsdlI3IHeU1/H2Lx+yrYT02w6hpH71Jum0hf3e1mlXD4mUuwvAkhZN74Ag7bPHAGdJQ3ShYMOIH7Q1LW40n1kPjAXUlkrkowyswcYP696Pr4Y8g7nG5jGdiTon00vlQRE1REMN64LAxo5hnPWX2/MNxFoUJTLOniBYawJR8LL1fM4HK96A+XfzU= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230016)(4636009)(376002)(136003)(346002)(396003)(39860400002)(40470700004)(36840700001)(46966006)(82310400005)(316002)(36860700001)(54906003)(40460700003)(110136005)(426003)(186003)(47076005)(36756003)(26005)(16526019)(34020700004)(336012)(7696005)(70206006)(4744005)(5660300002)(2906002)(8676002)(86362001)(1076003)(7416002)(478600001)(70586007)(81166007)(4326008)(6666004)(41300700001)(966005)(40480700001)(82740400003)(921005)(2616005)(356005)(8936002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jul 2022 16:51:57.5653 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aa90c8af-c751-48b2-a3d4-08da6039013b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR1201MB2482 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org This MSR can be used for controlling whether the CPU boost state is enabled in the hardware. AMD Processor Programming Reference (PPR) Link: https://www.amd.com/system/files/TechDocs/40332.pdf [p1095] Link: https://www.amd.com/system/files/TechDocs/56569-A1-PUB.zip [p162] Signed-off-by: Perry Yuan --- arch/x86/include/asm/msr-index.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index d27e0581b777..869508de8269 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -548,6 +548,7 @@ #define MSR_AMD_CPPC_CAP2 0xc00102b2 #define MSR_AMD_CPPC_REQ 0xc00102b3 #define MSR_AMD_CPPC_STATUS 0xc00102b4 +#define MSR_AMD_CPPC_HW_CTL 0xc0010015 #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff)