| Message ID | 20220707165137.211400-1-Perry.Yuan@amd.com |
|---|---|
| State | Superseded |
| Headers | show
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From: Perry Yuan <Perry.Yuan@amd.com>
To: <rafael.j.wysocki@intel.com>, <viresh.kumar@linaro.org>,
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Subject: [PATCH 01/12] x86/msr: Add the MSR definition for AMD CPPC hardware
control.
Date: Thu, 7 Jul 2022 12:51:36 -0400
Message-ID: <20220707165137.211400-1-Perry.Yuan@amd.com>
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|
| Series |
[01/12] x86/msr: Add the MSR definition for AMD CPPC hardware control.
|
expand
|
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index d27e0581b777..869508de8269 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -548,6 +548,7 @@ #define MSR_AMD_CPPC_CAP2 0xc00102b2 #define MSR_AMD_CPPC_REQ 0xc00102b3 #define MSR_AMD_CPPC_STATUS 0xc00102b4 +#define MSR_AMD_CPPC_HW_CTL 0xc0010015 #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff)
This MSR can be used for controlling whether the CPU boost state is enabled in the hardware. AMD Processor Programming Reference (PPR) Link: https://www.amd.com/system/files/TechDocs/40332.pdf [p1095] Link: https://www.amd.com/system/files/TechDocs/56569-A1-PUB.zip [p162] Signed-off-by: Perry Yuan <Perry.Yuan@amd.com> --- arch/x86/include/asm/msr-index.h | 1 + 1 file changed, 1 insertion(+)