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[92.40.169.177]) by smtp.gmail.com with ESMTPSA id c6-20020a170906170600b00706242d297fsm3738302eje.212.2022.06.18.14.39.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jun 2022 14:39:57 -0700 (PDT) From: Aidan MacDonald To: linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, wens@csie.org, jic23@kernel.org, lee.jones@linaro.org, sre@kernel.org, broonie@kernel.org, gregkh@linuxfoundation.org, lgirdwood@gmail.com Cc: lars@metafoo.de, rafael@kernel.org, quic_gurus@quicinc.com, sebastian.reichel@collabora.com, andy.shevchenko@gmail.com, michael@walle.cc, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 01/16] regmap-irq: Use sub_irq_reg() to calculate unmask register address Date: Sat, 18 Jun 2022 22:39:54 +0100 Message-Id: <20220618214009.2178567-2-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220618214009.2178567-1-aidanmacdonald.0x0@gmail.com> References: <20220618214009.2178567-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Call sub_irq_reg() instead of calculating the offset of the register to avoid relying on the fact that sub_irq_reg() is a linear function of "base_reg" and "i". Unmask registers were the only type that didn't use sub_irq_reg() for address calculation; thus, sub_irq_reg() is now the only method used to obtain register addresses. This prepares for allowing drivers to override the default sub_irq_reg implementation if the default behavior is unsuitable. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 400c7412a7dc..4a2e1f6aa94d 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -97,7 +97,6 @@ static void regmap_irq_sync_unlock(struct irq_data *data) struct regmap *map = d->map; int i, j, ret; u32 reg; - u32 unmask_offset; u32 val; if (d->chip->runtime_pm) { @@ -141,11 +140,11 @@ static void regmap_irq_sync_unlock(struct irq_data *data) dev_err(d->map->dev, "Failed to sync unmasks in %x\n", reg); - unmask_offset = d->chip->unmask_base - - d->chip->mask_base; + /* clear mask with unmask_base register */ + reg = sub_irq_reg(d, d->chip->unmask_base, i); ret = regmap_irq_update_bits(d, - reg + unmask_offset, + reg, d->mask_buf_def[i], d->mask_buf[i]); } else { @@ -632,7 +631,6 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, int ret = -ENOMEM; int num_type_reg; u32 reg; - u32 unmask_offset; if (chip->num_regs <= 0) return -EINVAL; @@ -773,10 +771,9 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, ret = regmap_irq_update_bits(d, reg, d->mask_buf[i], ~d->mask_buf[i]); else if (d->chip->unmask_base) { - unmask_offset = d->chip->unmask_base - - d->chip->mask_base; + reg = sub_irq_reg(d, d->chip->unmask_base, i); ret = regmap_irq_update_bits(d, - reg + unmask_offset, + reg, d->mask_buf[i], d->mask_buf[i]); } else