From patchwork Wed Jun 8 16:47:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chang S. Bae" X-Patchwork-Id: 580498 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C182CC433EF for ; Wed, 8 Jun 2022 17:11:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230042AbiFHRLp (ORCPT ); Wed, 8 Jun 2022 13:11:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230118AbiFHRK5 (ORCPT ); Wed, 8 Jun 2022 13:10:57 -0400 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 451D83FBBD6; Wed, 8 Jun 2022 09:56:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1654707413; x=1686243413; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=sxbD4J7BtSo1S6gF/v2H3MizySMBUhfYlLpZNaGXRBE=; b=igA7zG32F3DnDjcm9q0cIeak4QjSn1mSHZ2RwyGQDamk/cBTnB8RoONR mDyVoEvtXjq3LqvmWgX3/VSV7FTJWwSaTmkvML+NQTizfHS8LPPPZqlaj 1sQt7DCmMm1CkWJiBKrvW4VW+w03A9MOobIHFluZYkZReyEZbVS25SZYH 61wn2htgiFOhkU7M/Dqx7sjVlnFLwSCHZnvwuB2w0BZuS6bB4tRK7RfmK ygCMb6wSFY0xywO8jI0zmVGM1h3UXpY6wXuPBgjVMu/f/wclzIQ4NBSuk AKZtW4vYj9fgG4ZoudZe4r0ookApPZ/JK2RgF7hm84MH0BmpOC8qhRKhH A==; X-IronPort-AV: E=McAfee;i="6400,9594,10372"; a="265768320" X-IronPort-AV: E=Sophos;i="5.91,286,1647327600"; d="scan'208";a="265768320" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jun 2022 09:56:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,286,1647327600"; d="scan'208";a="585001343" Received: from chang-linux-3.sc.intel.com ([172.25.66.173]) by fmsmga007.fm.intel.com with ESMTP; 08 Jun 2022 09:56:52 -0700 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org, x86@kernel.org, linux-pm@vger.kernel.org Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, peterz@infradead.org, bp@alien8.de, rafael@kernel.org, riel@fb.com, bigeasy@linutronix.de, hch@lst.de, fenghua.yu@intel.com, rui.zhang@intel.com, artem.bityutskiy@linux.intel.com, jacob.jun.pan@linux.intel.com, lenb@kernel.org, chang.seok.bae@intel.com Subject: [PATCH v5 2/2] intel_idle: Add a new flag to initialize the AMX state Date: Wed, 8 Jun 2022 09:47:48 -0700 Message-Id: <20220608164748.11864-3-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220608164748.11864-1-chang.seok.bae@intel.com> References: <20220608164748.11864-1-chang.seok.bae@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The non-initialized AMX state can be the cause of C-state demotion from C6 to C1E. This low-power idle state may improve power savings and thus result in a higher available turbo frequency budget. This behavior is implementation-specific. Initialize the state for the C6 entrance of Sapphire Rapids as needed. Suggested-by: Peter Zijlstra (Intel) Signed-off-by: Chang S. Bae Tested-by : Zhang Rui Acked-by: Rafael J. Wysocki Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Artem Bityutskiy Cc: Jacob Pan Cc: Len Brown --- Changes from v2: * Remove an unnecessary backslash (Rafael Wysocki). Changes from v1: * Simplify the code with a new flag (Rui). * Rebase on Artem's patches for SPR intel_idle. * Massage the changelog. --- drivers/idle/intel_idle.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c index b9bb94bd0f67..5f36c4b28f9d 100644 --- a/drivers/idle/intel_idle.c +++ b/drivers/idle/intel_idle.c @@ -54,6 +54,7 @@ #include #include #include +#include #define INTEL_IDLE_VERSION "0.5.1" @@ -105,6 +106,11 @@ static unsigned int mwait_substates __initdata; */ #define CPUIDLE_FLAG_ALWAYS_ENABLE BIT(15) +/* + * Initialize large xstate for the C6-state entrance. + */ +#define CPUIDLE_FLAG_INIT_XSTATE BIT(16) + /* * MWAIT takes an 8-bit "hint" in EAX "suggesting" * the C-state (top nibble) and sub-state (bottom nibble) @@ -139,6 +145,9 @@ static __cpuidle int intel_idle(struct cpuidle_device *dev, if (state->flags & CPUIDLE_FLAG_IRQ_ENABLE) local_irq_enable(); + if (state->flags & CPUIDLE_FLAG_INIT_XSTATE) + fpu_idle_fpregs(); + mwait_idle_with_hints(eax, ecx); return index; @@ -159,8 +168,12 @@ static __cpuidle int intel_idle(struct cpuidle_device *dev, static __cpuidle int intel_idle_s2idle(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - unsigned long eax = flg2MWAIT(drv->states[index].flags); unsigned long ecx = 1; /* break on interrupt flag */ + struct cpuidle_state *state = &drv->states[index]; + unsigned long eax = flg2MWAIT(state->flags); + + if (state->flags & CPUIDLE_FLAG_INIT_XSTATE) + fpu_idle_fpregs(); mwait_idle_with_hints(eax, ecx); @@ -895,7 +908,8 @@ static struct cpuidle_state spr_cstates[] __initdata = { { .name = "C6", .desc = "MWAIT 0x20", - .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, + .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED | + CPUIDLE_FLAG_INIT_XSTATE, .exit_latency = 290, .target_residency = 800, .enter = &intel_idle,