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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Mar 2022 20:55:24.1546 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 47698720-300f-4789-29d8-08da10fd47b5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5908 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The comments in `acpi_pci_bridge_d3` make an assertion that all devices behind a PCIe root port that supports D3 also support D3. This was pointed out however that it's no guarantee but rather a reasonable assumption for the ecosystem used for Thunderbolt and USB4. Update the comment to use weaker language and clarifying this is an assumption. Suggested-by: Bjorn Helgaas Signed-off-by: Mario Limonciello --- v4->v5: * New patch drivers/pci/pci-acpi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 91c165ea4346..4f12d4fca808 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -989,8 +989,8 @@ bool acpi_pci_bridge_d3(struct pci_dev *dev) /* * The ACPI firmware will provide the device-specific properties through * _DSD configuration object. Look for the 'HotPlugSupportInD3' property - * for the root port and if it is set we know the hierarchy behind it - * supports D3 just fine. + * for the root port and if it is set we make an assumption that the + * hierarchy behind it supports D3 as well. */ rpdev = pcie_find_root_port(dev); if (!rpdev)