From patchwork Thu Feb 10 05:49:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 542002 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F232CC433F5 for ; Thu, 10 Feb 2022 05:51:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235154AbiBJFvu (ORCPT ); Thu, 10 Feb 2022 00:51:50 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:44930 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234985AbiBJFv0 (ORCPT ); Thu, 10 Feb 2022 00:51:26 -0500 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB0B81172 for ; Wed, 9 Feb 2022 21:51:18 -0800 (PST) Received: by mail-pl1-x62b.google.com with SMTP id p6so730926plf.10 for ; Wed, 09 Feb 2022 21:51:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Qlm9yJ5575SFpR6IPywQKZmVoP3waSVFMhfeayBNTbA=; b=fnfZc0AIG8SBxpjQDcaVBiRVbSpK8UXvadVoxtlMHcKr0gAVz662qCEZ2aLfHkaCrp oiNJ+9QqhvaLMKcfaPl1GvDq/YUj/KRrfqu1TELLhPgEcxVBKkh5/LP578h0s79b1qwj Y7SVefGUnaxDq3ntC/uarGxulVKTMh9zt2PhbZ5bJd2Bnb1UTvzXAAVcFv37EO3hG2OS z27IWz2UqxPidErtJ6MEhNTczwPVKRGCWbxEC3/KRbK/xRRz5GP8MTSv/3LDlLwfNba8 osTFlbhy2375IUn5yHEpNyCH1aSPSULs4Q4hVFjmfd5Opdfvh1Tc1WsDh0arV08b9I13 RBSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Qlm9yJ5575SFpR6IPywQKZmVoP3waSVFMhfeayBNTbA=; b=dgxug9JWJNHgc3qsG8KEh0ClSLVDKy2sipEMjam81EM04uOawBgZXlxAI+PDx2NMdi zDl1F80UgbVFfAlX1yAKfx6hFHVgeM7JZnpD6QKtxPUIP4DBxyLcaA36NohTaVbavJYK TZikY1MKfFAqbFMZOWbzfIRvDq+C6ACOWO0haeZTPzogKLZPqHyPuXsihUC5gT7JudIK Xdiezc1Ws+CUrTNcuccfBYe9bcjYCuM9Y8BXUQvf9AOie6w6cMIHcgNF/fsmUiIl9325 jZUfQQ4ytkC50nLH+oxQqIqeUbxknPdC++2rmMx380/1Vg2zjNJtskNXS/OG3g/E29Fl 6Eyw== X-Gm-Message-State: AOAM533Le0DW4BaknWuc9vaKQ+1zCpkWgoFZ+ZWZchF4gZEBcsEqevtX zHM13mZ+I+6AIAP2gWhwzCk+bw== X-Google-Smtp-Source: ABdhPJyfhOIllPegTmHNIO0ywUxfTTaD2VxDT95TmWoHMJ394XuWoV97b8eft+oMdipg7wKw+LoPoQ== X-Received: by 2002:a17:903:2406:: with SMTP id e6mr6077678plo.98.1644472278347; Wed, 09 Feb 2022 21:51:18 -0800 (PST) Received: from localhost.localdomain ([122.179.114.46]) by smtp.gmail.com with ESMTPSA id s32sm15192270pfw.80.2022.02.09.21.51.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Feb 2022 21:51:17 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano , Ulf Hansson , "Rafael J . Wysocki" , Pavel Machek , Rob Herring Cc: Sandeep Tripathy , Atish Patra , Alistair Francis , Liush , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvm-riscv@lists.infradead.org, Anup Patel Subject: [PATCH v11 8/8] RISC-V: Enable RISC-V SBI CPU Idle driver for QEMU virt machine Date: Thu, 10 Feb 2022 11:19:47 +0530 Message-Id: <20220210054947.170134-9-apatel@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210054947.170134-1-apatel@ventanamicro.com> References: <20220210054947.170134-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Anup Patel We enable RISC-V SBI CPU Idle driver for QEMU virt machine to test SBI HSM Supend on QEMU. Signed-off-by: Anup Patel Signed-off-by: Anup Patel --- arch/riscv/Kconfig.socs | 3 +++ arch/riscv/configs/defconfig | 1 + arch/riscv/configs/rv32_defconfig | 1 + 3 files changed, 5 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 6ec44a22278a..f4097a815201 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -36,6 +36,9 @@ config SOC_VIRT select GOLDFISH select RTC_DRV_GOLDFISH if RTC_CLASS select SIFIVE_PLIC + select PM_GENERIC_DOMAINS if PM + select PM_GENERIC_DOMAINS_OF if PM && OF + select RISCV_SBI_CPUIDLE if CPU_IDLE help This enables support for QEMU Virt Machine. diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index a5e0482a4969..b8c882b70b02 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -20,6 +20,7 @@ CONFIG_SOC_SIFIVE=y CONFIG_SOC_VIRT=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y +CONFIG_PM=y CONFIG_CPU_IDLE=y CONFIG_VIRTUALIZATION=y CONFIG_KVM=m diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig index d1b87db54d68..6f9a7c89bff9 100644 --- a/arch/riscv/configs/rv32_defconfig +++ b/arch/riscv/configs/rv32_defconfig @@ -20,6 +20,7 @@ CONFIG_SOC_VIRT=y CONFIG_ARCH_RV32I=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y +CONFIG_PM=y CONFIG_CPU_IDLE=y CONFIG_VIRTUALIZATION=y CONFIG_KVM=m