From patchwork Thu Jan 27 19:34:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 537837 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C632C43219 for ; Thu, 27 Jan 2022 19:33:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245596AbiA0TdI (ORCPT ); Thu, 27 Jan 2022 14:33:08 -0500 Received: from mga04.intel.com ([192.55.52.120]:47245 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231221AbiA0TdG (ORCPT ); Thu, 27 Jan 2022 14:33:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643311986; x=1674847986; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=d6aKRtAzjDjmJM2+973h3G8biktTSCUUKJusK0j5rXI=; b=CEQdM5q3cLq+z7jwiMXOvBPyGHTKGzI07nMK7u2zBHNAIC/q51WaWCGo huwx765yC6W5CCLP4XG7D09m5IHlzFJXPpxxwt6uVnSX/ERfXcm8XPMYV 2U3eB1aTMvj4X9Xg5v2+Vl0Dqx+VBGV5LVr6nnlPyk+QrUxQhlIny6Bmn wyE+4xlwFDja3E4+0vWJEsIBiO33mU30RQcbGkSyHlrhfak2v5dYYWpie CYpE7ILdHQmtXZqBeNaKj8isWQ8rKkjxUhmVfowmAP1d8wCXFKpcvpMuN xpRz+qKBwfQwjFFdkLJVY0x88p0hGwLMq5yq+xo7olDjMoGCu7WnSq1yJ A==; X-IronPort-AV: E=McAfee;i="6200,9189,10239"; a="245788383" X-IronPort-AV: E=Sophos;i="5.88,321,1635231600"; d="scan'208";a="245788383" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jan 2022 11:33:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,321,1635231600"; d="scan'208";a="495844896" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orsmga002.jf.intel.com with ESMTP; 27 Jan 2022 11:33:02 -0800 From: Ricardo Neri To: "Rafael J. Wysocki" , Daniel Lezcano , linux-pm@vger.kernel.org Cc: x86@kernel.org, linux-doc@vger.kernel.org, Len Brown , Srinivas Pandruvada , Aubrey Li , Amit Kucheria , Andi Kleen , Tim Chen , Lukasz Luba , "Ravi V. Shankar" , Ricardo Neri , linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH v5 2/7] x86/cpu: Add definitions for the Intel Hardware Feedback Interface Date: Thu, 27 Jan 2022 11:34:49 -0800 Message-Id: <20220127193454.12814-3-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220127193454.12814-1-ricardo.neri-calderon@linux.intel.com> References: <20220127193454.12814-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add the CPUID feature bit and the model-specific registers needed to identify and configure the Intel Hardware Feedback Interface. Cc: Andi Kleen Cc: Aubrey Li Cc: Len Brown Cc: Srinivas Pandruvada Cc: Tim Chen Cc: "Ravi V. Shankar" Acked-by: Borislav Petkov Signed-off-by: Ricardo Neri --- Changes since v4: * None Changes since v3: * None Changes since v2: * Replaced subject prefix to be "x86/cpu:". (Boris) Changes since v1: * Renamed X86_FEATURE_INTEL_HFI as X86_FEATURE_HFI. (Boris) --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/msr-index.h | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 6db4e2932b3d..b39f510128f3 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -330,6 +330,7 @@ #define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */ #define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */ #define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */ +#define X86_FEATURE_HFI (14*32+19) /* Hardware Feedback Interface */ /* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */ #define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 3faf0f97edb1..89e0a1d5ee36 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -704,12 +704,14 @@ #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) +#define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26) #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) +#define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25) /* Thermal Thresholds Support */ #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) @@ -958,4 +960,8 @@ #define MSR_VM_IGNNE 0xc0010115 #define MSR_VM_HSAVE_PA 0xc0010117 +/* Hardware Feedback Interface */ +#define MSR_IA32_HW_FEEDBACK_PTR 0x17d0 +#define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1 + #endif /* _ASM_X86_MSR_INDEX_H */