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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , Steven Rostedt , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v7 02/14] x86/msr: Add AMD CPPC MSR definitions Date: Fri, 24 Dec 2021 09:04:56 +0800 Message-ID: <20211224010508.110159-3-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211224010508.110159-1-ray.huang@amd.com> References: <20211224010508.110159-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 95151b69-0b07-49cd-596a-08d9c6798046 X-MS-TrafficTypeDiagnostic: MN2PR12MB2877:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1107; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: jwiw68eelmhjL1UhSIyxpQ5o03uuqA9zI8g6C0yXwdMDsPm7gUo5eLK3KOixbS2e2munGdRTXeH990TOv4x4l/NBhK4kQp/hmlbu/yHrHEZb2WP4Vu14pkRELSzx1dyAKNwQq/bQ4P+79KJpgO0Nr5fDTOPesbbFPIj79uIVpbIjhogPz5F7c9HE9vaPdbds1r7vMtLengSV/b7OsEDgX9pB7H1FGEyewpWQidCtz2b5VDmrmgcpwqRc0r3dQzCIy4uIEzNQkJ0vKl+75TFGi4ofUsXarNwuP0i1MKkCH6FOmCbf4/i/A7jUT1FomSz7W8vrFh70A/9S0T7Hxp37EwTIwpuXtiG3Uaha/qFMTsiCY7Es9Rq1Sv3+BfdscRg9s4eckBoYkSbTGKkvoG1PVYvh299Id6Mb5t55yw1jay92+X64p4BEYFAL1yK5/db+quEdSdB5ntgoCo+wAK3OGh6HRlXYmKo7mTCrcfwhDLokXcFcHaamsyfNwbEIH0lYvoaI3HQAcIf2R1d4wq4Aoh9agrn/F4wnIivTPMT0POzK3BdAGLT0qltPLr+ku++RU73BF1f+5OWfNxKd+2E1sxaXV9HrzvIV2CMxs0bnhO0GTR2+VdE8kCtpDeoO4/MAx1XLh94NQfrlSAHuKxDHqF6sPWoOF8dWlCSnvwrl80WXptRAofkZgvLsHP+Xq1A9FV/V9YN1AWYVHclL6JzgBSfCluYM6i8wBv/MiAHj1RAFltAD/0dSDzHf+it7lpaBnmWPtl9ZIQoc8Xps8vhNV9kGpUn17v1sxpPHSIulxcQ= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(40470700002)(40460700001)(86362001)(8936002)(8676002)(70206006)(316002)(2906002)(54906003)(70586007)(1076003)(7416002)(110136005)(6666004)(508600001)(82310400004)(7696005)(4326008)(47076005)(336012)(5660300002)(426003)(26005)(2616005)(356005)(186003)(16526019)(36756003)(36860700001)(81166007)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Dec 2021 01:05:39.4291 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 95151b69-0b07-49cd-596a-08d9c6798046 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT011.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB2877 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org AMD CPPC (Collaborative Processor Performance Control) function uses MSR registers to manage the performance hints. So add the MSR register macro here. Signed-off-by: Huang Rui Acked-by: Borislav Petkov --- arch/x86/include/asm/msr-index.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 01e2650b9585..3faf0f97edb1 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -486,6 +486,23 @@ #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f +/* AMD Collaborative Processor Performance Control MSRs */ +#define MSR_AMD_CPPC_CAP1 0xc00102b0 +#define MSR_AMD_CPPC_ENABLE 0xc00102b1 +#define MSR_AMD_CPPC_CAP2 0xc00102b2 +#define MSR_AMD_CPPC_REQ 0xc00102b3 +#define MSR_AMD_CPPC_STATUS 0xc00102b4 + +#define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) +#define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) +#define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff) +#define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff) + +#define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0) +#define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) +#define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) +#define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) + /* Fam 17h MSRs */ #define MSR_F17H_IRPERF 0xc00000e9