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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , Steven Rostedt , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v6 02/14] x86/msr: add AMD CPPC MSR definitions Date: Mon, 20 Dec 2021 00:35:16 +0800 Message-ID: <20211219163528.1023186-3-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211219163528.1023186-1-ray.huang@amd.com> References: <20211219163528.1023186-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9e029b3a-eea8-42f7-65ee-08d9c30da842 X-MS-TrafficTypeDiagnostic: CH2PR12MB4311:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1107; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: TP3M3/4UMgnW5g8xpvteolpHCawUTw8dtUBnkHZwb9l+Fk3l8Qn5phqoUP98eU3Ie4Juh61C6axxB4S2gWiG8FIHERa8cnV1SjzTVuPxZda4P8fbuJD9qqfcH/ymqVQnaXJrBaoD3Y/qEDRithxTOOt2nh6h7HVrdxWy870pWOskICh8KXafupu7uRBJi4AYB4n2ZFZo49p7+r9mqHVY9IApWwF430CFLLAj959xuz0Ac6XOTfT0N/OaevOaNkCxiDgkLm5CVRS7cy9jgCAij43jwYXEYxa+t9NvS+pMusXdYZ/sOMCNMhgExq36qhzKi2HVIJPAvfqYyFj1IShwA3l7A1FjRIgtp//7B9FeoAjVificlwefaD7tErnPCrEXntQaudgvKRsm+ajNJtAt119XzDiSPEKMHVUrD6F3gX31FPhIk+nIEJrpmxPdGPgfZVAyNTp4Q3eInROVN9k78AXhCHcY/FJNZ0gcVEZooZWPi8qeHxR+39uAeF4VICfoQtZNki6MkWoAa+aISSa16QpRz+fYM+zonFcYwD+JySVyvfH+2hucHySEi6BUyiLSyFKdCVe3213cJxUlMPfTVrP1XVxxTj6UbsoLulmVpg/TX59cbdVS/7KLpsNKxVCQL9RSe40dCUU7k1+HBmCuCUoEfDCNKp8Ia+wwwsYs/UMrBebnf1xyAty11SW3274Za2jklYus93+i56Pf4gwcS4PokfI5DMmTXGN5kTtL/d2ZXRUaYud2e5Uu3xGK5ch/MqxI+KsqhnGjjy687rCn1yyg4GA5FRMbUqtEVT8zpqs= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(40470700001)(1076003)(2906002)(7416002)(316002)(110136005)(5660300002)(36860700001)(86362001)(36756003)(70586007)(81166007)(356005)(4326008)(70206006)(508600001)(82310400004)(8936002)(47076005)(16526019)(186003)(6666004)(40460700001)(54906003)(7696005)(26005)(426003)(8676002)(336012)(2616005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2021 16:36:07.4111 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9e029b3a-eea8-42f7-65ee-08d9c30da842 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT043.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4311 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org AMD CPPC (Collaborative Processor Performance Control) function uses MSR registers to manage the performance hints. So add the MSR register macro here. Signed-off-by: Huang Rui --- arch/x86/include/asm/msr-index.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 01e2650b9585..e7945ef6a8df 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -486,6 +486,23 @@ #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f +/* AMD Collaborative Processor Performance Control MSRs */ +#define MSR_AMD_CPPC_CAP1 0xc00102b0 +#define MSR_AMD_CPPC_ENABLE 0xc00102b1 +#define MSR_AMD_CPPC_CAP2 0xc00102b2 +#define MSR_AMD_CPPC_REQ 0xc00102b3 +#define MSR_AMD_CPPC_STATUS 0xc00102b4 + +#define CAP1_LOWEST_PERF(x) (((x) >> 0) & 0xff) +#define CAP1_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) +#define CAP1_NOMINAL_PERF(x) (((x) >> 16) & 0xff) +#define CAP1_HIGHEST_PERF(x) (((x) >> 24) & 0xff) + +#define REQ_MAX_PERF(x) (((x) & 0xff) << 0) +#define REQ_MIN_PERF(x) (((x) & 0xff) << 8) +#define REQ_DES_PERF(x) (((x) & 0xff) << 16) +#define REQ_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) + /* Fam 17h MSRs */ #define MSR_F17H_IRPERF 0xc00000e9