From patchwork Sun Sep 12 20:54:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Krzyszkowiak X-Patchwork-Id: 510101 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D549FC433FE for ; Sun, 12 Sep 2021 20:54:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B7C2A6103D for ; Sun, 12 Sep 2021 20:54:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236137AbhILUzk (ORCPT ); Sun, 12 Sep 2021 16:55:40 -0400 Received: from comms.puri.sm ([159.203.221.185]:32776 "EHLO comms.puri.sm" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236129AbhILUzk (ORCPT ); Sun, 12 Sep 2021 16:55:40 -0400 Received: from localhost (localhost [127.0.0.1]) by comms.puri.sm (Postfix) with ESMTP id 6ED6FE030C; Sun, 12 Sep 2021 13:54:25 -0700 (PDT) Received: from comms.puri.sm ([127.0.0.1]) by localhost (comms.puri.sm [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id U2GGkN6HnWPj; Sun, 12 Sep 2021 13:54:24 -0700 (PDT) From: Sebastian Krzyszkowiak To: Sebastian Reichel , linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Anton Vorontsov , Ramakrishna Pallala , Dirk Brandewie , Sebastian Krzyszkowiak , stable@vger.kernel.org Subject: [PATCH 1/2] power: supply: max17042_battery: Clear status bits in interrupt handler Date: Sun, 12 Sep 2021 22:54:01 +0200 Message-Id: <20210912205402.160939-1-sebastian.krzyszkowiak@puri.sm> Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The gauge requires us to clear the status bits manually for some alerts to be properly dismissed. Previously the IRQ was configured to react only on falling edge, which wasn't technically correct (the ALRT line is active low), but it had a happy side-effect of preventing interrupt storms on uncleared alerts from happening. Fixes: 7fbf6b731bca ("power: supply: max17042: Do not enforce (incorrect) interrupt trigger type") Cc: Signed-off-by: Sebastian Krzyszkowiak --- drivers/power/supply/max17042_battery.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/power/supply/max17042_battery.c b/drivers/power/supply/max17042_battery.c index 8dffae76b6a3..c53980c8432a 100644 --- a/drivers/power/supply/max17042_battery.c +++ b/drivers/power/supply/max17042_battery.c @@ -876,6 +876,9 @@ static irqreturn_t max17042_thread_handler(int id, void *dev) max17042_set_soc_threshold(chip, 1); } + regmap_clear_bits(chip->regmap, MAX17042_STATUS, + 0xFFFF & ~(STATUS_POR_BIT | STATUS_BST_BIT)); + power_supply_changed(chip->battery); return IRQ_HANDLED; }