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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Ingo Molnar , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH 06/19] cpufreq: amd: add acpi cppc function as the backend for legacy processors Date: Wed, 8 Sep 2021 22:59:48 +0800 Message-ID: <20210908150001.3702552-7-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210908150001.3702552-1-ray.huang@amd.com> References: <20210908150001.3702552-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 219fec5b-6fad-4734-3d6a-08d972d980ad X-MS-TrafficTypeDiagnostic: CH2PR12MB4860: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3383; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: CDaNJZnvnMbm/XMsYvBAGMi3AXlNkUJlkKevn8MhAXdFf13xXFw2Qg4BBghTh2sD20RbkJy8dLRzWexKDgYRsztQ8MUvGI1a3iVILds6JJtd2I+zzJY2Hw//tkPscEwPJ0pMn/42tCdy/NWgQmmnh+88aTzyY2mUl7/g5XhVwSqjnzQo7ywEkmhXIXa9SDrH/68cHDQrxh40IoQKpBdcCA3I93qSH3CooBKaW6BRJYnUqL2KcRx9H9NdCc50aECkEBJzJUE3q6bUrLhgYhrmiJwvsVno3muoFGj4Ycm1of2AIs+hZ9ES+1oi6P1sG4eTLG7Df1CTl81ZsDg7IPaql+pwFEjx959XfvrZzhCOEAvUPx9ScmjfoSUzdNzm4aQiL0X79RG4YUrIM+K/fCchU76KqL5tMANERzDD2tCtl4CalLNMjs7bgkQ12w5iojNmrUILd/xMAM17lg8t5DtMgFMAAddqAgk4+PdI/jHsRw3EaEmEhcPEH/Nn9RC6oFm7SaVFKVulOYhmUK81Bo5LH9PemyBeJzf4lK3aPx/IM/U/hP9fKQro3j/22tDKeRFY2/UAvUt+RHttnQcVmrqCb5HZvgslmqNzSqzy+auF4UpoupzTkUjn2puSUDhS9ApgEiEeKeyJUS0iVs1IEZZZIKN/ZiFRViDEcbDHXT9XqXQa5WV04jBlgDWhh3InmIQ6vHppqx3ldo55+oXIKTSJXtny5PU8cHSL2Cidc/BTBu4= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(47076005)(70206006)(316002)(8676002)(7696005)(81166007)(54906003)(336012)(356005)(8936002)(426003)(110136005)(83380400001)(2616005)(4326008)(86362001)(508600001)(36756003)(186003)(5660300002)(1076003)(16526019)(26005)(2906002)(70586007)(82310400003)(6666004)(36860700001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2021 15:01:14.0303 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 219fec5b-6fad-4734-3d6a-08d972d980ad X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT036.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4860 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org In some old Zen based processors, they are using the shared memory that exposed from ACPI SBIOS. Signed-off-by: Jinzhou Su Signed-off-by: Huang Rui --- drivers/cpufreq/amd-pstate.c | 63 ++++++++++++++++++++++++++++++++---- 1 file changed, 57 insertions(+), 6 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 32b4f6d79783..a46cd5dd9f7c 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -82,6 +82,19 @@ static inline int pstate_enable(bool enable) return wrmsrl_safe(MSR_AMD_CPPC_ENABLE, enable ? 1 : 0); } +static int cppc_enable(bool enable) +{ + int cpu, ret = 0; + + for_each_online_cpu(cpu) { + ret = cppc_set_enable(cpu, enable ? 1 : 0); + if (ret) + return ret; + } + + return ret; +} + static int amd_pstate_enable(struct amd_pstate_perf_funcs *funcs, bool enable) { @@ -113,6 +126,24 @@ static int pstate_init_perf(struct amd_cpudata *cpudata) return 0; } +static int cppc_init_perf(struct amd_cpudata *cpudata) +{ + struct cppc_perf_caps cppc_perf; + + int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); + if (ret) + return ret; + + WRITE_ONCE(cpudata->highest_perf, amd_get_highest_perf()); + + WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf); + WRITE_ONCE(cpudata->lowest_nonlinear_perf, + cppc_perf.lowest_nonlinear_perf); + WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf); + + return 0; +} + static int amd_pstate_init_perf(struct amd_cpudata *cpudata) { struct amd_pstate_perf_funcs *funcs = cpufreq_get_driver_data(); @@ -134,6 +165,19 @@ static void pstate_update_perf(struct amd_cpudata *cpudata, READ_ONCE(cpudata->cppc_req_cached)); } +static void cppc_update_perf(struct amd_cpudata *cpudata, + u32 min_perf, u32 des_perf, + u32 max_perf, bool fast_switch) +{ + struct cppc_perf_ctrls perf_ctrls; + + perf_ctrls.max_perf = max_perf; + perf_ctrls.min_perf = min_perf; + perf_ctrls.desired_perf = des_perf; + + cppc_set_perf(cpudata->cpu, &perf_ctrls); +} + static int amd_pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf, u32 des_perf, u32 max_perf, bool fast_switch) @@ -370,6 +414,12 @@ static struct amd_pstate_perf_funcs pstate_funcs = { .update_perf = pstate_update_perf, }; +static struct amd_pstate_perf_funcs cppc_funcs = { + .enable = cppc_enable, + .init_perf = cppc_init_perf, + .update_perf = cppc_update_perf, +}; + static int amd_pstate_cpu_init(struct cpufreq_policy *policy) { int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; @@ -416,7 +466,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) /* It will be updated by governor */ policy->cur = policy->cpuinfo.min_freq; - policy->fast_switch_possible = true; + if (boot_cpu_has(X86_FEATURE_AMD_CPPC_EXT)) + policy->fast_switch_possible = true; ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0], FREQ_QOS_MIN, policy->cpuinfo.min_freq); @@ -471,7 +522,6 @@ static struct cpufreq_driver amd_pstate_driver = { .verify = amd_pstate_verify, .target = amd_pstate_target, .fast_switch = amd_pstate_fast_switch, - .adjust_perf = amd_pstate_adjust_perf, .init = amd_pstate_cpu_init, .exit = amd_pstate_cpu_exit, .name = "amd-pstate", @@ -496,14 +546,15 @@ static int __init amd_pstate_init(void) return -EEXIST; /* capability check */ - if (!boot_cpu_has(X86_FEATURE_AMD_CPPC_EXT)) { + if (boot_cpu_has(X86_FEATURE_AMD_CPPC_EXT)) { pr_debug("%s, AMD CPPC extension functionality is supported\n", __func__); - return -ENODEV; + funcs = &pstate_funcs; + amd_pstate_driver.adjust_perf = amd_pstate_adjust_perf; + } else { + funcs = &cppc_funcs; } - funcs = &pstate_funcs; - /* enable amd pstate feature */ ret = amd_pstate_enable(funcs, true); if (ret) {