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[109.252.193.159]) by smtp.gmail.com with ESMTPSA id r27sm1225823lfn.290.2020.11.22.16.31.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Nov 2020 16:31:13 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: [PATCH v10 01/19] dt-bindings: memory: tegra20: emc: Document opp-supported-hw property Date: Mon, 23 Nov 2020 03:27:05 +0300 Message-Id: <20201123002723.28463-2-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201123002723.28463-1-digetx@gmail.com> References: <20201123002723.28463-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Document opp-supported-hw property, which is not strictly necessary to have on Tegra20, but it's very convenient to have because all other SoC core devices will use hardware versioning, and thus, it's good to maintain the consistency. Signed-off-by: Dmitry Osipenko --- .../bindings/memory-controllers/nvidia,tegra20-emc.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt index 67ac8d1297da..fe99ce1013bd 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt @@ -16,6 +16,12 @@ Properties: - #interconnect-cells : Should be 0. - operating-points-v2: See ../bindings/opp/opp.txt for details. +For each opp entry in 'operating-points-v2' table: +- opp-supported-hw: One bitfield indicating SoC process ID mask + + A bitwise AND is performed against this value and if any bit + matches, the OPP gets enabled. + Optional properties: - core-supply: Phandle of voltage regulator of the SoC "core" power domain.