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[79.139.237.54]) by smtp.gmail.com with ESMTPSA id e21sm3650953ljb.135.2020.06.07.11.57.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Jun 2020 11:57:42 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen Cc: =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v3 25/39] ARM: tegra: Add interconnect properties to Tegra20 device-tree Date: Sun, 7 Jun 2020 21:55:16 +0300 Message-Id: <20200607185530.18113-26-digetx@gmail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200607185530.18113-1-digetx@gmail.com> References: <20200607185530.18113-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add interconnect properties to the memory controller, external memory controller and the display controller nodes in order to describe hardware interconnection. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20.dtsi | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index c3b8ad53b967..974048e83541 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -109,6 +109,15 @@ dc@54200000 { nvidia,head = <0>; + interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, + <&mc TEGRA20_MC_DISPLAY0B &emc>, + <&mc TEGRA20_MC_DISPLAY0C &emc>, + <&mc TEGRA20_MC_DISPLAY1B &emc>; + interconnect-names = "display0a", + "display0b", + "display0c", + "display1b"; + rgb { status = "disabled"; }; @@ -126,6 +135,15 @@ dc@54240000 { nvidia,head = <1>; + interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, + <&mc TEGRA20_MC_DISPLAY0BB &emc>, + <&mc TEGRA20_MC_DISPLAY0CB &emc>, + <&mc TEGRA20_MC_DISPLAY1BB &emc>; + interconnect-names = "display0a", + "display0b", + "display0c", + "display1b"; + rgb { status = "disabled"; }; @@ -626,15 +644,17 @@ mc: memory-controller@7000f000 { interrupts = ; #reset-cells = <1>; #iommu-cells = <0>; + #interconnect-cells = <1>; }; - memory-controller@7000f400 { + emc: memory-controller@7000f400 { compatible = "nvidia,tegra20-emc"; reg = <0x7000f400 0x200>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_EMC>; #address-cells = <1>; #size-cells = <0>; + #interconnect-cells = <0>; }; fuse@7000f800 {