Message ID | 20200330010904.27643-5-digetx@gmail.com |
---|---|
State | New |
Headers | show |
Series | Introduce memory interconnect for NVIDIA Tegra SoCs | expand |
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml index e4135bac6957..2d7aed245552 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml @@ -31,6 +31,9 @@ properties: interrupts: maxItems: 1 + "#interconnect-cells": + const: 0 + nvidia,memory-controller: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -217,6 +220,7 @@ required: - interrupts - clocks - nvidia,memory-controller + - "#interconnect-cells" additionalProperties: false @@ -230,6 +234,8 @@ examples: nvidia,memory-controller = <&mc>; + #interconnect-cells = <0>; + emc-timings-1 { nvidia,ram-code = <1>;
External memory controller is interconnected with memory controller and with external memory. Document new interconnect property which turns external memory controller into interconnect provider. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- .../bindings/memory-controllers/nvidia,tegra30-emc.yaml | 6 ++++++ 1 file changed, 6 insertions(+)