[v2,22/22] ARM: multi_v7_defconfig: Enable interconnect API

Message ID	20200330010904.27643-23-digetx@gmail.com
State	New
Headers	show Return-Path: <SRS0=kFxE=5P=vger.kernel.org=linux-pm-owner@kernel.org> From: Dmitry Osipenko <digetx@gmail.com> To: Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= <a.swigon@samsung.com>, Georgi Djakov <georgi.djakov@linaro.org>, Rob Herring <robh+dt@kernel.org> Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 22/22] ARM: multi_v7_defconfig: Enable interconnect API Date: Mon, 30 Mar 2020 04:09:04 +0300 Message-Id: <20200330010904.27643-23-digetx@gmail.com> In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-pm-owner@vger.kernel.org Precedence: bulk
Series	Introduce memory interconnect for NVIDIA Tegra SoCs \| expand [v2,00/22] Introduce memory interconnect for NVIDIA Tegra SoCs [v2,02/22] dt-bindings: memory: tegra20: emc: Document new interconnect property [v2,04/22] dt-bindings: memory: tegra30: emc: Document new interconnect property [v2,06/22] dt-bindings: memory: tegra20: Add memory client IDs [v2,08/22] ARM: tegra: Add interconnect properties to Tegra20 device-tree [v2,09/22] ARM: tegra: Add interconnect properties to Tegra30 device-tree [v2,10/22] interconnect: Relax requirement in of_icc_get_from_provider() [v2,14/22] memory: tegra20-emc: Register as interconnect provider [v2,15/22] memory: tegra20-emc: Create tegra20-devfreq device [v2,16/22] memory: tegra30-emc: Continue probing if timings are missing in device-tree [v2,21/22] ARM: tegra: Enable interconnect API in tegra_defconfig [v2,22/22] ARM: multi_v7_defconfig: Enable interconnect API

Message ID

20200330010904.27643-23-digetx@gmail.com

State

New

Headers

From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter
	<jonathanh@nvidia.com>, =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?=
	<a.swigon@samsung.com>, Georgi Djakov <georgi.djakov@linaro.org>,
	Rob Herring <robh+dt@kernel.org>
Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org,
	linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	devicetree@vger.kernel.org
Subject: [PATCH v2 22/22] ARM: multi_v7_defconfig: Enable interconnect API
Date: Mon, 30 Mar 2020 04:09:04 +0300
Message-Id: <20200330010904.27643-23-digetx@gmail.com>
In-Reply-To: <20200330010904.27643-1-digetx@gmail.com>
References: <20200330010904.27643-1-digetx@gmail.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Sender: linux-pm-owner@vger.kernel.org
Precedence: bulk

Series

Introduce memory interconnect for NVIDIA Tegra SoCs | expand

Commit Message

Dmitry Osipenko March 30, 2020, 1:09 a.m. UTC

NVIDIA Tegra now has interconnect providers that are used for memory
bandwidth allocation.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 arch/arm/configs/multi_v7_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index f8e45351c3f9..658b5c1892eb 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -1085,6 +1085,7 @@  CONFIG_FSI_MASTER_ASPEED=m
 CONFIG_FSI_SCOM=m
 CONFIG_FSI_SBEFIFO=m
 CONFIG_FSI_OCC=m
+CONFIG_INTERCONNECT=y
 CONFIG_EXT4_FS=y
 CONFIG_AUTOFS4_FS=y
 CONFIG_MSDOS_FS=y

[v2,22/22] ARM: multi_v7_defconfig: Enable interconnect API

Commit Message

Patch