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Thu, 22 Apr 2021 20:30:57 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 22 Apr 2021 13:30:56 -0700 Received: from skomatineni-linux.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 22 Apr 2021 20:30:56 +0000 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH 4/4] arm64: dts: tegra194: Add CPU idle states Date: Thu, 22 Apr 2021 13:30:48 -0700 Message-ID: <1619123448-10138-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1619123448-10138-1-git-send-email-skomatineni@nvidia.com> References: <1619123448-10138-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bb6b35f2-6993-41f6-dad8-08d905cd891e X-MS-TrafficTypeDiagnostic: DM6PR12MB2940: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:262; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Apr 2021 20:30:57.4832 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bb6b35f2-6993-41f6-dad8-08d905cd891e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.32]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT011.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2940 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org This patch adds CPU core and cluster idle states to Tegra194 device tree Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 9449156..c3b478e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2161,6 +2161,7 @@ device_type = "cpu"; reg = <0x000>; enable-method = "psci"; + cpu-idle-states = <&C6>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; @@ -2175,6 +2176,7 @@ device_type = "cpu"; reg = <0x001>; enable-method = "psci"; + cpu-idle-states = <&C6>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; @@ -2189,6 +2191,7 @@ device_type = "cpu"; reg = <0x100>; enable-method = "psci"; + cpu-idle-states = <&C6>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; @@ -2203,6 +2206,7 @@ device_type = "cpu"; reg = <0x101>; enable-method = "psci"; + cpu-idle-states = <&C6>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; @@ -2217,6 +2221,7 @@ device_type = "cpu"; reg = <0x200>; enable-method = "psci"; + cpu-idle-states = <&C6>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; @@ -2231,6 +2236,7 @@ device_type = "cpu"; reg = <0x201>; enable-method = "psci"; + cpu-idle-states = <&C6>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; @@ -2245,6 +2251,7 @@ device_type = "cpu"; reg = <0x300>; enable-method = "psci"; + cpu-idle-states = <&C6>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; @@ -2259,6 +2266,7 @@ device_type = "cpu"; reg = <0x301>; enable-method = "psci"; + cpu-idle-states = <&C6>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; @@ -2343,6 +2351,17 @@ cache-line-size = <64>; cache-sets = <4096>; }; + + idle-states { + entry-method = "arm,psci"; + C6: c6 { + compatible = "arm,idle-state"; + wakeup-latency-us = <2000>; + min-residency-us = <30000>; + arm,psci-suspend-param = <0x6>; + status = "okay"; + }; + }; }; psci {