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Mon, 25 Jan 2021 17:34:33 +0000 Subject: [PATCH v2 1/8] cpupower: Update msr_pstate union struct naming From: Nathan Fontenot To: rrichter@amd.com, shuah@kernel.org, linux-kernel@vger.kernel.org, trenn@suse.com, linux-pm@vger.kernel.org Cc: boris.ostrovsky@oracle.com, joao.m.martins@oracle.com, konrad.wilk@oracle.com Date: Mon, 25 Jan 2021 11:34:36 -0600 Message-ID: <161159607626.68367.14656572319107224636.stgit@ethanol01c7-host.amd.com> In-Reply-To: <161159600371.68367.14890273216040482793.stgit@ethanol01c7-host.amd.com> References: <161159600371.68367.14890273216040482793.stgit@ethanol01c7-host.amd.com> User-Agent: StGit/0.17.1-dirty X-Originating-IP: [165.204.78.2] X-ClientProxiedBy: SN4PR0601CA0023.namprd06.prod.outlook.com (2603:10b6:803:2f::33) To SN6PR12MB4720.namprd12.prod.outlook.com (2603:10b6:805:e6::31) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from ethanol01c7-host.amd.com (165.204.78.2) by SN4PR0601CA0023.namprd06.prod.outlook.com (2603:10b6:803:2f::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3784.12 via Frontend Transport; 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PTR:; CAT:NONE; SFS:(4636009)(396003)(366004)(39860400002)(376002)(346002)(136003)(316002)(186003)(26005)(103116003)(2906002)(15650500001)(16526019)(8676002)(44832011)(52116002)(7696005)(956004)(8936002)(83380400001)(55016002)(966005)(86362001)(4326008)(478600001)(5660300002)(66556008)(66476007)(66946007); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: =?utf-8?q?78OBylJKZCUeu/8ZCvt7c9pUYKb?= =?utf-8?q?2ufErHcEVoB9hGiRHKL/pmlGeCiXKS6RkbaxVk0E0pnI69BEWbvu6677?= =?utf-8?q?NgiIGZ4LDGKRnZD6eC4YYdL0Y+i/zDHBddRkXTB0WRk8OCV03WfArd+9?= =?utf-8?q?mKTDwzc+LweEhiiiO5UlF7n2GSGUKPR59ZjJHorEoC9hxQ+mXgCyyD6/?= =?utf-8?q?76RPJgrYzRw5GPy/OD/Re3x6bJTp3SQLn+Edmd5N/FPiAQCPU41CaZA7?= =?utf-8?q?rL9DaEE3y75ukFbKsIqi+oJKXmsvjRkzd77Au2SvtTL+wp6dM2N2iCd0?= =?utf-8?q?aQlAIyWCuiUI8vAtRzldkMtA5GtgH/g9SD1MSrx2g9kUba/pSwkaRtTw?= =?utf-8?q?jZ7Wc1cqt2tezCNBEyNLWe7GtuGWSfD7UqMeOVHQ+gkDRX4Q9Ayp6phv?= =?utf-8?q?mll5usAEV3tvw+2PAS9An++o7FOnp30UWpLi5u9PCyYrlXA/3Q/a4NSx?= =?utf-8?q?uTtLxJ94ryGd4Kd9VYBB4yX83rdISfeayim+lYj1G1Vt5fAeIrmx+ll2?= =?utf-8?q?G76WfmfW2qYk4a62ptj6VK3QdKVzXN+vny72zmaPmUII6HviruoJBcec?= =?utf-8?q?DPdkF/a4ZxMcfYpBBOufe3Y43czjrUN8XLeQ7KR7m5MxBPqtKmy7uR0I?= =?utf-8?q?wcG9koDqA4cUPiwgAKD+xamKVlFZm3Pjy140gKj2Yb6PGgqL7RFVOBBW?= =?utf-8?q?Vl1xN9UJGikda6pVE3oumT4MtGIkGUV51U/gmrHQS+6UuKugde8pxTWp?= =?utf-8?q?zwp/Vb56DjZ4IytZweKh+u9wPVJKPd85+t5/lHHPHwg3HHUR0jauXInO?= =?utf-8?q?TwEIKWl4hCfGdDonDRbIIDPWo/DD/vxRyHmuFW5My2neouoLH69fObzt?= =?utf-8?q?ak0NrDOz96lppmD/gEmOIQNAudQQbRwB4JHD5ocPFTZpeA9SRi2dt3Gy?= =?utf-8?q?WjFmWnMoe1Pu1rWZmQhcpLUm9GT9mZh1WqMZXull+4CXikbrwmfXIwVU?= =?utf-8?q?EsxFz+w83i+1C5m4sCf4+PyZ6GbTtOFJQ4L9X2a2I4xZ4WCY5BY2wCwc?= =?utf-8?q?nQH4RJ2ZqptU+t++UNH5EOdo96Aw48fsrx3QRTg9zUh+UHF/1gViL?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 03d4efe0-8362-4d95-eeeb-08d8c1577a43 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB4720.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jan 2021 17:34:33.2042 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: nG7MyG7Gs+5si3AH+ZHi8yut+Wue5YFMtI0n+E0oG58Tq3NQsbm5kxqUE4gE1Pb2yf86YumUcEMY8xk1dZIGpw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2765 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The msr_pstate union struct named fam17h_bits is misleading since this is the struct to use for all families >= 0x17, not just for family 0x17. Rename the bits structs to be 'pstate' (for pre family 17h CPUs) and 'pstatedef' (for CPUs since fam 17h) to align closer with PPR/BDKG (1) naming. There are no functional changes as part of this update. 1: AMD Processor Programming Reference (PPR) and BIOS and Kernel Developer's Guide (BKDG) available at: http://developer.amd.com/resources/developer-guides-manuals Signed-off-by: Nathan Fontenot --- Updates for v2: Add links to PPR/BKDG in commit message --- tools/power/cpupower/utils/helpers/amd.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/tools/power/cpupower/utils/helpers/amd.c b/tools/power/cpupower/utils/helpers/amd.c index 7c4f83a8c973..34368436bbd6 100644 --- a/tools/power/cpupower/utils/helpers/amd.c +++ b/tools/power/cpupower/utils/helpers/amd.c @@ -13,7 +13,8 @@ #define MSR_AMD_PSTATE 0xc0010064 #define MSR_AMD_PSTATE_LIMIT 0xc0010061 -union msr_pstate { +union core_pstate { + /* pre fam 17h: */ struct { unsigned fid:6; unsigned did:3; @@ -26,7 +27,8 @@ union msr_pstate { unsigned idddiv:2; unsigned res3:21; unsigned en:1; - } bits; + } pstate; + /* since fam 17h: */ struct { unsigned fid:8; unsigned did:6; @@ -35,36 +37,36 @@ union msr_pstate { unsigned idddiv:2; unsigned res1:31; unsigned en:1; - } fam17h_bits; + } pstatedef; unsigned long long val; }; -static int get_did(int family, union msr_pstate pstate) +static int get_did(int family, union core_pstate pstate) { int t; if (family == 0x12) t = pstate.val & 0xf; else if (family == 0x17 || family == 0x18) - t = pstate.fam17h_bits.did; + t = pstate.pstatedef.did; else - t = pstate.bits.did; + t = pstate.pstate.did; return t; } -static int get_cof(int family, union msr_pstate pstate) +static int get_cof(int family, union core_pstate pstate) { int t; int fid, did, cof; did = get_did(family, pstate); if (family == 0x17 || family == 0x18) { - fid = pstate.fam17h_bits.fid; + fid = pstate.pstatedef.fid; cof = 200 * fid / did; } else { t = 0x10; - fid = pstate.bits.fid; + fid = pstate.pstate.fid; if (family == 0x11) t = 0x8; cof = (100 * (fid + t)) >> did; @@ -89,7 +91,7 @@ int decode_pstates(unsigned int cpu, unsigned int cpu_family, int boost_states, unsigned long *pstates, int *no) { int i, psmax, pscur; - union msr_pstate pstate; + union core_pstate pstate; unsigned long long val; /* Only read out frequencies from HW when CPU might be boostable @@ -119,9 +121,9 @@ int decode_pstates(unsigned int cpu, unsigned int cpu_family, } if (read_msr(cpu, MSR_AMD_PSTATE + i, &pstate.val)) return -1; - if ((cpu_family == 0x17) && (!pstate.fam17h_bits.en)) + if ((cpu_family == 0x17) && (!pstate.pstatedef.en)) continue; - else if (!pstate.bits.en) + else if (!pstate.pstate.en) continue; pstates[i] = get_cof(cpu_family, pstate);