From patchwork Fri Oct 23 08:24:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hector Yuan X-Patchwork-Id: 286741 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.1 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2E22C388F9 for ; Fri, 23 Oct 2020 08:25:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 78B152192A for ; Fri, 23 Oct 2020 08:25:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="GnQ6+fAV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S460548AbgJWIZO (ORCPT ); Fri, 23 Oct 2020 04:25:14 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:39521 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S460537AbgJWIZM (ORCPT ); Fri, 23 Oct 2020 04:25:12 -0400 X-UUID: 8546ccb3dd9a4aabbb4c3beabb0f73bc-20201023 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=rCMbXAuODNB8y7MkCaQc2mt7ayxf9TpGQeinPyFrbEU=; b=GnQ6+fAVumYrFWqAkKKLjk9CLJtjVadZpNeJwhDfjYydGS1aZnF1QMeozaJX9Zw8G04Z+olQvmVI4ZSLOUD/SgZBmMYIwYtdwMtrXDd2w+51FZ+CsKgiRmveywJHUPVKTiwcRSVK5AXgj7pW/nx220aWyFUmeuNxb6q2mmRCYKc=; X-UUID: 8546ccb3dd9a4aabbb4c3beabb0f73bc-20201023 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 436456902; Fri, 23 Oct 2020 16:25:00 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Oct 2020 16:24:59 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 23 Oct 2020 16:24:59 +0800 From: Hector Yuan To: , , , Rob Herring , "Rafael J. Wysocki" , Viresh Kumar , Maxime Ripard , Santosh Shilimkar , Amit Kucheria , Stephen Boyd , Ulf Hansson , Dave Gerlach , Florian Fainelli , Robin Murphy , Lorenzo Pieralisi , CC: , , Subject: [PATCH v1 4/6] cpufreq: mediatek-hw: register EM power table Date: Fri, 23 Oct 2020 16:24:51 +0800 Message-ID: <1603441493-18554-5-git-send-email-hector.yuan@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1603441493-18554-1-git-send-email-hector.yuan@mediatek.com> References: <1603441493-18554-1-git-send-email-hector.yuan@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 1492DA2F4D89FE5D46D7253A3B77EFCEF5EC965C4A22111D57C163518DC29DF22000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: "Hector.Yuan" Register energy model table for EAS and thermal cooling device usage Signed-off-by: Hector.Yuan --- drivers/cpufreq/mediatek-cpufreq-hw.c | 58 ++++++++++++++++++++++++++------- 1 file changed, 46 insertions(+), 12 deletions(-) -- 1.7.9.5 diff --git a/drivers/cpufreq/mediatek-cpufreq-hw.c b/drivers/cpufreq/mediatek-cpufreq-hw.c index 74449da..241d93f 100644 --- a/drivers/cpufreq/mediatek-cpufreq-hw.c +++ b/drivers/cpufreq/mediatek-cpufreq-hw.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -17,9 +18,10 @@ #define LUT_ROW_SIZE 0x4 enum { - REG_LUT_TABLE, - REG_ENABLE, - REG_PERF_STATE, + REG_FREQ_LUT_TABLE, + REG_FREQ_ENABLE, + REG_FREQ_PERF_STATE, + REG_EM_POWER_TBL, REG_ARRAY_SIZE, }; @@ -27,23 +29,44 @@ enum { struct cpufreq_mtk { struct cpufreq_frequency_table *table; void __iomem *reg_bases[REG_ARRAY_SIZE]; + int nr_opp; cpumask_t related_cpus; }; static const u16 cpufreq_mtk_offsets[REG_ARRAY_SIZE] = { - [REG_LUT_TABLE] = 0x0, - [REG_ENABLE] = 0x84, - [REG_PERF_STATE] = 0x88, + [REG_FREQ_LUT_TABLE] = 0x0, + [REG_FREQ_ENABLE] = 0x84, + [REG_FREQ_PERF_STATE] = 0x88, + [REG_EM_POWER_TBL] = 0x3D0, }; static struct cpufreq_mtk *mtk_freq_domain_map[NR_CPUS]; +static int mtk_cpufreq_get_cpu_power(unsigned long *mW, + unsigned long *KHz, struct device *cpu_dev) +{ + struct cpufreq_mtk *c = mtk_freq_domain_map[cpu_dev->id]; + int i; + + for (i = 0; i < c->nr_opp; i++) { + if (c->table[i].frequency < *KHz) + break; + } + i--; + + *KHz = c->table[i].frequency; + *mW = readl_relaxed(c->reg_bases[REG_EM_POWER_TBL] + + i * LUT_ROW_SIZE) / 1000; + + return 0; +} + static int mtk_cpufreq_hw_target_index(struct cpufreq_policy *policy, unsigned int index) { struct cpufreq_mtk *c = policy->driver_data; - writel_relaxed(index, c->reg_bases[REG_PERF_STATE]); + writel_relaxed(index, c->reg_bases[REG_FREQ_PERF_STATE]); return 0; } @@ -55,7 +78,7 @@ static unsigned int mtk_cpufreq_hw_get(unsigned int cpu) c = mtk_freq_domain_map[cpu]; - index = readl_relaxed(c->reg_bases[REG_PERF_STATE]); + index = readl_relaxed(c->reg_bases[REG_FREQ_PERF_STATE]); index = min(index, LUT_MAX_ENTRIES - 1); return c->table[index].frequency; @@ -64,6 +87,14 @@ static unsigned int mtk_cpufreq_hw_get(unsigned int cpu) static int mtk_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) { struct cpufreq_mtk *c; + struct device *cpu_dev; + struct em_data_callback em_cb = EM_DATA_CB(mtk_cpufreq_get_cpu_power); + + cpu_dev = get_cpu_device(policy->cpu); + if (!cpu_dev) { + pr_err("failed to get cpu%d device\n", policy->cpu); + return -ENODEV; + } c = mtk_freq_domain_map[policy->cpu]; if (!c) { @@ -77,7 +108,9 @@ static int mtk_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) policy->driver_data = c; /* HW should be in enabled state to proceed now */ - writel_relaxed(0x1, c->reg_bases[REG_ENABLE]); + writel_relaxed(0x1, c->reg_bases[REG_FREQ_ENABLE]); + + em_dev_register_perf_domain(cpu_dev, c->nr_opp, &em_cb, policy->cpus); return 0; } @@ -93,7 +126,7 @@ static int mtk_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy) } /* HW should be in paused state now */ - writel_relaxed(0x0, c->reg_bases[REG_ENABLE]); + writel_relaxed(0x0, c->reg_bases[REG_FREQ_ENABLE]); return 0; } @@ -122,7 +155,7 @@ static int mtk_cpu_create_freq_table(struct platform_device *pdev, if (!c->table) return -ENOMEM; - base_table = c->reg_bases[REG_LUT_TABLE]; + base_table = c->reg_bases[REG_FREQ_LUT_TABLE]; for (i = 0; i < LUT_MAX_ENTRIES; i++) { data = readl_relaxed(base_table + (i * LUT_ROW_SIZE)); @@ -140,6 +173,7 @@ static int mtk_cpu_create_freq_table(struct platform_device *pdev, } c->table[i].frequency = CPUFREQ_TABLE_END; + c->nr_opp = i; return 0; } @@ -191,7 +225,7 @@ static int mtk_cpu_resources_init(struct platform_device *pdev, if (IS_ERR(base)) return PTR_ERR(base); - for (i = REG_LUT_TABLE; i < REG_ARRAY_SIZE; i++) + for (i = REG_FREQ_LUT_TABLE; i < REG_ARRAY_SIZE; i++) c->reg_bases[i] = base + offsets[i]; ret = mtk_get_related_cpus(index, c);