From patchwork Mon Sep 14 03:04:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 256783 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.1 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCC27C43461 for ; Mon, 14 Sep 2020 03:07:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A3A0A208FE for ; Mon, 14 Sep 2020 03:07:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="LOwnzn/f" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725982AbgINDHD (ORCPT ); Sun, 13 Sep 2020 23:07:03 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:11909 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726101AbgINDFI (ORCPT ); Sun, 13 Sep 2020 23:05:08 -0400 X-UUID: 97479aa049b745d29a36f550cc59269e-20200914 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=qBymKk2B0d56MBUuX1hhxF1oOlrZkobktKD1Mxr60CM=; b=LOwnzn/f2IBWb1u0l93sQygelWPh+i2U0sAZdNWUWpvEuVYvi4QoFG8zLzPcRDd84fCbVjXnXn8oyxEYCwEyrdDk6Myp2Njs0VyVWwXErdpCfP9u01yzg7qFxMtn5DSgK2/9U2U5bfkDwt4FUm6GR9Axg0PYpVSObwmz8eHTFaw=; X-UUID: 97479aa049b745d29a36f550cc59269e-20200914 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2002533154; Mon, 14 Sep 2020 11:04:50 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 14 Sep 2020 11:04:47 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 14 Sep 2020 11:04:47 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Viresh Kumar , Stephen Boyd , Ryan Case , Mark Brown CC: Mark Rutland , Nicolas Boichat , Fan Chen , James Liao , Arvin Wang , Mike Turquette , , , , , , Henry Chen Subject: [PATCH V5 04/17] arm64: dts: mt8183: add performance state support of scpsys Date: Mon, 14 Sep 2020 11:04:31 +0800 Message-ID: <1600052684-21198-5-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1600052684-21198-1-git-send-email-henryc.chen@mediatek.com> References: <1600052684-21198-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add support for performance state of scpsys on mt8183 platform Signed-off-by: Henry Chen --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) -- 1.9.1 diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index d85bae7..82ca929 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -12,6 +12,7 @@ #include #include #include "mt8183-pinfunc.h" +#include / { compatible = "mediatek,mt8183"; @@ -340,6 +341,27 @@ #address-cells = <1>; #size-cells = <0>; + operating-points-v2 = <&dvfsrc_opp_table>; + dvfsrc_opp_table: opp-table { + compatible = "operating-points-v2-level"; + + dvfsrc_vol_min: opp1 { + opp,level = ; + }; + + dvfsrc_freq_medium: opp2 { + opp,level = ; + }; + + dvfsrc_freq_max: opp3 { + opp,level = ; + }; + + dvfsrc_vol_max: opp4 { + opp,level = ; + }; + }; + audio@MT8183_POWER_DOMAIN_AUDIO { reg = ; };