From patchwork Mon Sep 14 03:04:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 256786 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.1 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB757C43461 for ; Mon, 14 Sep 2020 03:05:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9758D221E7 for ; Mon, 14 Sep 2020 03:05:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="dzCiJCPE" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726115AbgINDFP (ORCPT ); Sun, 13 Sep 2020 23:05:15 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:35987 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726105AbgINDFL (ORCPT ); Sun, 13 Sep 2020 23:05:11 -0400 X-UUID: fe5ed44f85de406f83c6fe252e68f761-20200914 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=nOOM9yhncstnm5UMFYqxtAtm4GAlmiu3+ZgwHqj+zAM=; b=dzCiJCPEb/5+CFfoRt5fzPpcsC4wK/qsTPnvqvXcnpQtTkI1EnARo6jsRziDF9sZhXhwkGEdYa6YCamuDQNs2GAIhBrXprn+8XzqFWSg1pvsA56s1qaYlYm1/xja2dktphn0fyg0UWjUxNVqWFjI+PK8KlmrsBpxJW2puMutbUI=; X-UUID: fe5ed44f85de406f83c6fe252e68f761-20200914 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 453261723; Mon, 14 Sep 2020 11:04:50 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 14 Sep 2020 11:04:48 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 14 Sep 2020 11:04:48 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Viresh Kumar , Stephen Boyd , Ryan Case , Mark Brown CC: Mark Rutland , Nicolas Boichat , Fan Chen , James Liao , Arvin Wang , Mike Turquette , , , , , , Henry Chen Subject: [PATCH V5 09/17] dt-bindings: interconnect: add MT8183 interconnect dt-bindings Date: Mon, 14 Sep 2020 11:04:36 +0800 Message-ID: <1600052684-21198-10-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1600052684-21198-1-git-send-email-henryc.chen@mediatek.com> References: <1600052684-21198-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add interconnect provider dt-bindings for MT8183. Signed-off-by: Henry Chen --- .../devicetree/bindings/soc/mediatek/dvfsrc.txt | 2 ++ include/dt-bindings/interconnect/mtk,mt8183-emi.h | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 include/dt-bindings/interconnect/mtk,mt8183-emi.h -- 1.9.1 diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt index d5a47d8..76ca61d 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt @@ -14,6 +14,7 @@ Required Properties: - clock-names: Must include the following entries: "dvfsrc": DVFSRC module clock - clocks: Must contain an entry for each entry in clock-names. +- #interconnect-cells : should contain 1 Example: @@ -22,4 +23,5 @@ Example: reg = <0 0x10012000 0 0x1000>; clocks = <&infracfg CLK_INFRA_DVFSRC>; clock-names = "dvfsrc"; + #interconnect-cells = <1>; }; diff --git a/include/dt-bindings/interconnect/mtk,mt8183-emi.h b/include/dt-bindings/interconnect/mtk,mt8183-emi.h new file mode 100644 index 0000000..2a54856 --- /dev/null +++ b/include/dt-bindings/interconnect/mtk,mt8183-emi.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT8183_EMI_H +#define __DT_BINDINGS_INTERCONNECT_MTK_MT8183_EMI_H + +#define MT8183_SLAVE_DDR_EMI 0 +#define MT8183_MASTER_MCUSYS 1 +#define MT8183_MASTER_GPU 2 +#define MT8183_MASTER_MMSYS 3 +#define MT8183_MASTER_MM_VPU 4 +#define MT8183_MASTER_MM_DISP 5 +#define MT8183_MASTER_MM_VDEC 6 +#define MT8183_MASTER_MM_VENC 7 +#define MT8183_MASTER_MM_CAM 8 +#define MT8183_MASTER_MM_IMG 9 +#define MT8183_MASTER_MM_MDP 10 + +#endif