From patchwork Wed Jun 22 19:36:45 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 70689 Delivered-To: patch@linaro.org Received: by 10.140.28.4 with SMTP id 4csp75007qgy; Wed, 22 Jun 2016 12:38:10 -0700 (PDT) X-Received: by 10.98.93.65 with SMTP id r62mr35934583pfb.114.1466624270989; Wed, 22 Jun 2016 12:37:50 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k126si1404443pfc.180.2016.06.22.12.37.50; Wed, 22 Jun 2016 12:37:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-pm-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752123AbcFVTht (ORCPT + 14 others); Wed, 22 Jun 2016 15:37:49 -0400 Received: from mail-pf0-f170.google.com ([209.85.192.170]:33725 "EHLO mail-pf0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751286AbcFVThs (ORCPT ); Wed, 22 Jun 2016 15:37:48 -0400 Received: by mail-pf0-f170.google.com with SMTP id i123so20522604pfg.0 for ; Wed, 22 Jun 2016 12:37:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Cl3H/4yjQaJeshth7qE3v/r0hRKCS1sJM07oKGiMWx4=; b=j7U/jzTNVpHRni48pQr1hQaWzjjZGN+nCGMfTqM13PMN7zKD5uUoG/hR3L/j1BORLG jE9AbzfnCei10cWJ1AwEFMx21fCFo4PV96cnd+C3BAtKOrWt43V5tP6c+Hk7qM8h+VGx QBP/EmTDiuu9oosCUnifV6b6f3D0V9vyBxpXY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Cl3H/4yjQaJeshth7qE3v/r0hRKCS1sJM07oKGiMWx4=; b=Aiw9wfMVHG3XaTlfX+elhDOb8OCHFJpsuRWsypyWhYdamVCjs5nvJdrorJE4TpqpAG 1rzooVApYhYc8O3LkEesCGq9BILP60EXXUEt14I56S2wBfHRfN+58e1HsAro7XNHu8NM TrvLdYIJZqeTF1cBd+toC/WRcUggyPHTV9px5CpmLFUEdPuzZitXTnhCfTGw4atSuoQJ HdF8w1gImkHJnW7O2BBFNfQn+Bdd0T/LJvdFfWhZDyCQiE2Gct++Bm0B+DbhnJHLqo+F 2U08y907BOxeJI9dPFz9Uc66FkAZO2p9O0eUQd4d0LphcwIg1hlv1ytPN3iFILKyw9Ws q/Ng== X-Gm-Message-State: ALyK8tKfP3jV8bQBJf+rC9/EYsTCrOuagcm0v6IpjpOc6z8MwGB2crp/vZ7eEm6uFJe822yj X-Received: by 10.98.13.206 with SMTP id 75mr5314787pfn.161.1466624267720; Wed, 22 Jun 2016 12:37:47 -0700 (PDT) Received: from ubuntu.localdomain ([172.56.9.151]) by smtp.gmail.com with ESMTPSA id t4sm1563368paw.32.2016.06.22.12.37.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 22 Jun 2016 12:37:46 -0700 (PDT) From: Lina Iyer To: ulf.hansson@linaro.org, khilman@kernel.org, rjw@rjwysocki.net, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: geert@linux-m68k.org, k.kozlowski@samsung.com, andy.gross@linaro.org, sboyd@codeaurora.org, linux-arm-msm@vger.kernel.org, lorenzo.pieralisi@arm.com, ahaslam@baylibre.com, mtitinger@baylibre.com, Lina Iyer Subject: [PATCH 10/14] doc / cpu_domains: Describe CPU PM domains setup and governor Date: Wed, 22 Jun 2016 13:36:45 -0600 Message-Id: <1466624209-27432-11-git-send-email-lina.iyer@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1466624209-27432-1-git-send-email-lina.iyer@linaro.org> References: <1466624209-27432-1-git-send-email-lina.iyer@linaro.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org A generic CPU PM domain functionality is provided by drivers/base/power/cpu_domains.c. This document describes the generic usecase of CPU's PM domains, the setup of such domains and a CPU specific genpd governor. Signed-off-by: Lina Iyer --- Documentation/power/cpu_domains.txt | 79 +++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 Documentation/power/cpu_domains.txt -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe linux-pm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/power/cpu_domains.txt b/Documentation/power/cpu_domains.txt new file mode 100644 index 0000000..bd99e92 --- /dev/null +++ b/Documentation/power/cpu_domains.txt @@ -0,0 +1,79 @@ +CPU PM domains +============== + +Newer CPUs are grouped in SoCs as clusters. A cluster in addition to the CPUs +may have caches, floating point units and other architecture specific power +controller that share resources when any of the CPUs are active. When the CPUs +are in idle, some of these cluster components may also idle. A cluster may +also be nested inside another cluster that provides common coherency +interfaces to share data between the clusters. The organization of such +clusters and CPU may be descibed in DT, since they are SoC specific. + +CPUIdle framework enables the CPUs to determine the sleep time and enter low +power state to save power during periods of idle. CPUs in a cluster may enter +and exit idle state independently of each other. During the time when all the +CPUs are in idle state, the cluster may safely put some of the shared +resources in their idle state. The time between the last CPU to enter idle and +the first CPU to wake up is the time available for the cluster to enter its +idle state. + +When SoCs power down the CPU during cpuidle, they generally have supplemental +hardware that can handshake with the CPU with a signal that indicates that the +CPU has stopped execution. The hardware is also responsible for warm booting +the CPU on receiving an interrupt. In a cluster architecture, common resources +that are shared by a cluster may also be powered down by an external +microcontroller or a processor. The microcontroller may be programmed in +advance to put the hardware blocks in a low power state, when the last active +CPU sends the idle signal. When the signal is received, the microcontroller +may trigger the hardware blocks to enter their low power state. When an +interrupt to wakeup the processor is received, the microcontroller is +responsible for bringing up the hardware blocks to its active state, before +waking up the CPU. The timelines for such operations should be in the +acceptable range for for CPU idle to get power benefits. + +CPU PM Domain Setup +------------------- + +PM domains are represented in the DT as domain consumers and providers. A +device may have a domain provider and a domain provider may support multiple +domain consumers. Domains like clusters, may also be nested inside one +another. A domain that has no active consumer, may be powered off and any +resuming consumer would trigger the domain back to active. Parent domains may +be powered off when the child domains are powered off. The CPU cluster can be +fashioned as a PM domain. When the CPU devices are powered off, the PM domain +may be powered off. + +Device idle is reference counted by runtime PM. When there is no active need +for the device, runtime PM invokes callbacks to suspend the parent domain. +Generic PM domain (genpd) handles the hierarchy of devices, domains and the +reference counting of objects leading to last man down and first man up in the +domain. The CPU domains helper functions defines PM domains for each CPU +cluster and attaches the CPU devices to the respective PM domains. + +Platform drivers may use the following API to register their CPU PM domains. + +of_setup_cpu_pd() - +Provides a single step registration of the CPU PM domain and attach CPUs to +the genpd. Platform drivers may additionally register callbacks for power_on +and power_off operations for the PM domain. + +of_setup_cpu_pd_single() - +Define PM domain for a single CPU and attach the CPU to its domain. + + +CPU PM Domain governor +---------------------- + +CPUs have a unique ability to determine their next wakeup. CPUs may wake up +for known timer interrupts and unknown interrupts from idle. Prediction +algorithms and heuristic based algorithms like the Menu governor for cpuidle +can determine the next wakeup of the CPU. However, determining the wakeup +across a group of CPUs is a tough problem to solve. + +A simplistic approach would be to resort to known wakeups of the CPUs in +determining the next wakeup of any CPU in the cluster. The CPU PM domain +governor does just that. By looking into the tick device of the CPUs, the +governor can determine the sleep time between the last CPU and the first +scheduled wakeup of any CPU in that domain. This combined with the PM QoS +requirement for CPU_DMA_LATENCY can be used to determine the deepest possible +idle state of the CPU domain.