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[209.132.180.67]) by mx.google.com with ESMTP id dy5si8425832pab.142.2015.12.26.22.22.21; Sat, 26 Dec 2015 22:22:21 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-pm-owner@vger.kernel.org; dkim=neutral (body hash did not verify) header.i=@linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752059AbbL0GWU (ORCPT + 11 others); Sun, 27 Dec 2015 01:22:20 -0500 Received: from mail-pf0-f180.google.com ([209.85.192.180]:36002 "EHLO mail-pf0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751718AbbL0GWT (ORCPT ); Sun, 27 Dec 2015 01:22:19 -0500 Received: by mail-pf0-f180.google.com with SMTP id 65so53118919pff.3 for ; Sat, 26 Dec 2015 22:22:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XeBvzwrD0k26A3GAc/Eh0kSpf9pNbNJNemUMsrBbv5Q=; b=QAByK1oEVLdff0fKX3sbFsDTRKEgowOB57Cp8GzY7VF1wFgKfSDZhCnigaFpf/O4/v 6AU+DY3QcThsr+R/v2NIhodMnNbzwKniG8peuXPOBidRh+p7ACchWSipyWh+b3sb6O01 +GU2hQxWdH6DSsk2tvUXPqturbcPBM2hl9QF8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XeBvzwrD0k26A3GAc/Eh0kSpf9pNbNJNemUMsrBbv5Q=; b=LRr3jiXRspiO81btJmTsZC6yAWCUyIZYySpV+Qhf+o4Vqgej20FvnNIcloQfvimpvk jdalXyAg2l7mz3QpY+ZYWd3Hj8C/b1khFKy1DpQp32KYcY6wZtoT69p4VSvhjzUFz/sR 3C0SqmRER8MzfF6Lx7kF7TMiRXN3vUkOSNaY1o40EvPw6TkhSdBxQQEcBYaqqio2ZTu3 5wArKOZxPlkkg3+8ParsH4Hiottdxf+VTYLPoC0l0mufF7VroVqMf4Q3Byz5IOwuQ7Sx 1GEE6yyaNjljqCywL0qT+PBGBqBMgs1RmB0mYjjwFOAIfI8khj8rikq7xXemC+T0xZmb 3iGQ== X-Gm-Message-State: ALoCoQnSweQeuYOu6s5DP/QvhjbvHFgPEbWMMwTsPeqn0jScw0Kx3HNwlLywYcltc+nwqHecfT1tJthdtvVQP/pyiCJTud48oQ== X-Received: by 10.98.73.7 with SMTP id w7mr69201332pfa.158.1451197338911; Sat, 26 Dec 2015 22:22:18 -0800 (PST) Received: from localhost.localdomain ([124.219.30.17]) by smtp.googlemail.com with ESMTPSA id tu9sm73508609pac.0.2015.12.26.22.22.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 26 Dec 2015 22:22:18 -0800 (PST) From: Pi-Cheng Chen To: Viresh Kumar , Matthias Brugger Cc: Michael Turquette , Daniel Kurtz , linux-mediatek@lists.infradead.org, linaro-kernel@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 3/3] ARM64: dts: mt8173: Add CPU OPP, clock and regulator supply properties Date: Sun, 27 Dec 2015 14:21:58 +0800 Message-Id: <1451197318-12418-4-git-send-email-pi-cheng.chen@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1451197318-12418-1-git-send-email-pi-cheng.chen@linaro.org> References: <1451197318-12418-1-git-send-email-pi-cheng.chen@linaro.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add operating-points-v2, clock, and regulator supply properties required by mt8173-cpufreq driver to enable it. Signed-off-by: Pi-Cheng Chen --- This patch is based on the patch[1] that adds underlying clock MUX for MT8173 which is needed by mt8173-cpufreq driver but not yet picked. [1] http://article.gmane.org/gmane.linux.kernel.clk/325 --- arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 18 ++++++ arch/arm64/boot/dts/mediatek/mt8173.dtsi | 90 +++++++++++++++++++++++++++++ 2 files changed, 108 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-pm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index 811cb76..5b6321b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -405,6 +405,24 @@ status = "okay"; }; +&cpu0 { + proc-supply = <&mt6397_vpca15_reg>; +}; + +&cpu1 { + proc-supply = <&mt6397_vpca15_reg>; +}; + +&cpu2 { + proc-supply = <&da9211_vcpu_reg>; + sram-supply = <&mt6397_vsramca7_reg>; +}; + +&cpu3 { + proc-supply = <&da9211_vcpu_reg>; + sram-supply = <&mt6397_vsramca7_reg>; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 4dd5f93..ae28c12 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -24,6 +24,80 @@ #address-cells = <2>; #size-cells = <2>; + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + opp@507000000 { + opp-hz = /bits/ 64 <507000000>; + opp-microvolt = <859000>; + }; + opp@702000000 { + opp-hz = /bits/ 64 <702000000>; + opp-microvolt = <908000>; + }; + opp@1001000000 { + opp-hz = /bits/ 64 <1001000000>; + opp-microvolt = <983000>; + }; + opp@1105000000 { + opp-hz = /bits/ 64 <1105000000>; + opp-microvolt = <1009000>; + }; + opp@1183000000 { + opp-hz = /bits/ 64 <1183000000>; + opp-microvolt = <1028000>; + }; + opp@1404000000 { + opp-hz = /bits/ 64 <1404000000>; + opp-microvolt = <1083000>; + }; + opp@1508000000 { + opp-hz = /bits/ 64 <1508000000>; + opp-microvolt = <1109000>; + }; + opp@1573000000 { + opp-hz = /bits/ 64 <1573000000>; + opp-microvolt = <1125000>; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + opp@507000000 { + opp-hz = /bits/ 64 <507000000>; + opp-microvolt = <828000>; + }; + opp@702000000 { + opp-hz = /bits/ 64 <702000000>; + opp-microvolt = <867000>; + }; + opp@1001000000 { + opp-hz = /bits/ 64 <1001000000>; + opp-microvolt = <927000>; + }; + opp@1209000000 { + opp-hz = /bits/ 64 <1209000000>; + opp-microvolt = <968000>; + }; + opp@1404000000 { + opp-hz = /bits/ 64 <1404000000>; + opp-microvolt = <1007000>; + }; + opp@1612000000 { + opp-hz = /bits/ 64 <1612000000>; + opp-microvolt = <1049000>; + }; + opp@1807000000 { + opp-hz = /bits/ 64 <1807000000>; + opp-microvolt = <1089000>; + }; + opp@1989000000 { + opp-hz = /bits/ 64 <1989000000>; + opp-microvolt = <1125000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -54,6 +128,10 @@ reg = <0x000>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&infracfg CLK_INFRA_CA53SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@1 { @@ -62,6 +140,10 @@ reg = <0x001>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&infracfg CLK_INFRA_CA53SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@100 { @@ -70,6 +152,10 @@ reg = <0x100>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&infracfg CLK_INFRA_CA57SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; }; cpu3: cpu@101 { @@ -78,6 +164,10 @@ reg = <0x101>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&infracfg CLK_INFRA_CA57SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; }; idle-states {