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[209.132.180.67]) by mx.google.com with ESMTP id w12-v6si489834pld.362.2018.09.12.02.54.23; Wed, 12 Sep 2018 02:54:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J9L6R4gf; spf=pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-pm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727798AbeILO6I (ORCPT + 10 others); Wed, 12 Sep 2018 10:58:08 -0400 Received: from mail-ed1-f65.google.com ([209.85.208.65]:38340 "EHLO mail-ed1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727795AbeILO6I (ORCPT ); Wed, 12 Sep 2018 10:58:08 -0400 Received: by mail-ed1-f65.google.com with SMTP id h33-v6so1260938edb.5 for ; Wed, 12 Sep 2018 02:54:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=p+l9eG3EJUvs5PqroE1oN9/c9Y5I3RjwbnuwyKuwaKQ=; b=J9L6R4gfDqVWuTaZEOBoz4A2w3TIHW5Klx19orLgDv4Sl9La0s0FWXmR7JLmcigpEW DKdX1UdAg4XCcBHHnA6xPilTPpyQPnTZrgTwqHzUH+7yNsz7VXqCYTy2XnAIoSuRiR5R Wtnd7im10Eb7dMJnSui63aISD1ETTo4synyUs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=p+l9eG3EJUvs5PqroE1oN9/c9Y5I3RjwbnuwyKuwaKQ=; b=YG/0ImXE/tIVDLe9WsCbcxc0tgus8QGcRBjolc96dMkCDiEk377YvcgH6ooz+2nyls TLmZ4i3MGQH7Bfg07YZhy29tmcOrSAEzEPJaMSN4nIXmE50Lul3GX4XcmRvp/Yc5P3SQ JwQzHvUqswdbB/SD79YSyMvIs/QSUDBvEND8votcaoJ4mQJCbZtqte1Hhaj1Lx1y2f8S atXfnWhYXcQD5nOA6CilxPcWqP2rBW8/dJ7Yb4ffzgSaN97g4GFHZYEkIpEu371Yfn40 28knbVA7p9e8jFI1wjxM9XJYiA2MAPUCj9xvzmKxAbzD7rE5PFELzOZ4eews2fQvGt2Z kYlw== X-Gm-Message-State: APzg51Bc4lt1jI9UZ9Q5y5s7Vf3ojTCaizqYlz6yLdEDjYB1w34puQjz BD/MNIZG0nJHkzxqPz6lp6snWA== X-Received: by 2002:a50:de03:: with SMTP id z3-v6mr1749903edk.245.1536746060744; Wed, 12 Sep 2018 02:54:20 -0700 (PDT) Received: from localhost ([49.248.190.214]) by smtp.gmail.com with ESMTPSA id f13-v6sm690554edf.50.2018.09.12.02.54.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 12 Sep 2018 02:54:19 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: rnayak@codeaurora.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, smohanad@codeaurora.org, andy.gross@linaro.org, dianders@chromium.org, mka@chromium.org, Zhang Rui , Daniel Lezcano , linux-pm@vger.kernel.org Subject: [PATCH v3 08/16] thermal: tsens: Check if the IP is correctly enabled by firmware Date: Wed, 12 Sep 2018 15:22:53 +0530 Message-Id: <140b054230a61e13995ae4b685746c8faf068d61.1536744310.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The SROT registers are initialised by the secure firmware at boot. We don't have write access to the registers. Check if the block is enabled before continuing. Signed-off-by: Amit Kucheria Reviewed-by: Bjorn Andersson --- drivers/thermal/qcom/tsens-common.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index 0b8a793f15f4..3be4be2e0465 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -12,6 +12,10 @@ #include #include "tsens.h" +/* SROT */ +#define TSENS_EN BIT(0) + +/* TM */ #define STATUS_OFFSET 0x30 #define SN_ADDR_OFFSET 0x4 #define SN_ST_TEMP_MASK 0x3ff @@ -119,7 +123,10 @@ int __init init_common(struct tsens_device *tmdev) { void __iomem *tm_base, *srot_base; struct resource *res; + u32 code; + int ret; struct platform_device *op = of_find_device_by_node(tmdev->dev->of_node); + u16 ctrl_offset = tmdev->reg_offsets[SROT_CTRL_OFFSET]; if (!op) return -EINVAL; @@ -151,5 +158,15 @@ int __init init_common(struct tsens_device *tmdev) if (IS_ERR(tmdev->tm_map)) return PTR_ERR(tmdev->tm_map); + if (tmdev->srot_map) { + ret = regmap_read(tmdev->srot_map, ctrl_offset, &code); + if (ret) + return ret; + if (!(code & TSENS_EN)) { + dev_err(tmdev->dev, "tsens device is not enabled\n"); + return -ENODEV; + } + } + return 0; }