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[209.132.180.67]) by mx.google.com with ESMTP id ff3si19960358pbd.167.2014.07.28.22.32.10 for ; Mon, 28 Jul 2014 22:32:10 -0700 (PDT) Received-SPF: none (google.com: linux-samsung-soc-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752035AbaG2FcC (ORCPT + 6 others); Tue, 29 Jul 2014 01:32:02 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:25214 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752028AbaG2Fb7 (ORCPT ); Tue, 29 Jul 2014 01:31:59 -0400 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N9G006BPKP93030@mailout1.samsung.com>; Tue, 29 Jul 2014 14:31:57 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.126]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id 85.66.15745.DC137D35; Tue, 29 Jul 2014 14:31:57 +0900 (KST) X-AuditID: cbfee691-b7f306d000003d81-33-53d731cd61b5 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 92.57.05196.CC137D35; Tue, 29 Jul 2014 14:31:57 +0900 (KST) Received: from chromebld-server.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N9G0060UKOOEC80@mmp2.samsung.com>; Tue, 29 Jul 2014 14:31:56 +0900 (KST) From: Thomas Abraham To: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org, mturquette@linaro.org, kgene.kim@samsung.com, t.figa@samsung.com, l.majewski@samsung.com, viresh.kumar@linaro.org, thomas.ab@samsung.com, heiko@sntech.de, cw00.choi@samsung.com Subject: [PATCH v8 6/6] clk: samsung: remove unused clock aliases and update clock flags Date: Tue, 29 Jul 2014 10:58:31 +0530 Message-id: <1406611711-25112-7-git-send-email-thomas.ab@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1406611711-25112-1-git-send-email-thomas.ab@samsung.com> References: <1406611711-25112-1-git-send-email-thomas.ab@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupgkeLIzCtJLcpLzFFi42JZI2JSp3vW8HqwwcqPAhbXvzxntfj/6DWr Re+Cq2wWbx5uZrTY9Pgaq8Xn3iOMFjPO72OyeDrhIpvF+hmvWSw6ljFabPzq4cDtcefaHjaP zUvqPfq2rGL02H5tHrPH501yAaxRXDYpqTmZZalF+nYJXBkNCy6zFPxyq5jUs5e5gXGnTRcj J4eEgInExAt/2SBsMYkL99YD2VwcQgJLGSUeNv5hhCk6Pn0FO0RiOqPE13PrmSCcCUwSO1f9 YAepYhPQkbjx5jdYh4iAk8S3I9fAipgF7jJKHHv4DSwhLBAlcXn9FWYQm0VAVeLpmjtgNq+A q8TV+Z+BbA6gdQoScyaBnccp4CbR/PoG2HwhoJIfJ66wgMyUENjELrHrw32oOQIS3yYfYoHo lZXYdIAZ4mpJiYMrbrBMYBRewMiwilE0tSC5oDgpvchUrzgxt7g0L10vOT93EyMwFk7/ezZx B+P9A9aHGJOBxk1klhJNzgfGUl5JvKGxmZGFqYmpsZG5pRlpwkrivOmPkoKEBNITS1KzU1ML Uovii0pzUosPMTJxcEo1MHoz7ta0eqRnY72taMLGKPfTIcrfjinyr7VMP8WRVNd7YK23quhb /V6WrEOv59xSNJKx1NkvV6Az76aQSValqFNyj/OsWXwJoqteWHQp6FnNXjs5PpN9nditoxu+ u2UmhCeqBf+qklgWUuk1ay/Xv80Zh44s+3tEbZ5ZUsXVyfXxyrd+5wa9VGIpzkg01GIuKk4E ACvhlN+bAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrOIsWRmVeSWpSXmKPExsVy+t9jQd2zhteDDY6/YbO4/uU5q8X/R69Z LXoXXGWzePNwM6PFpsfXWC0+9x5htJhxfh+TxdMJF9ks1s94zWLRsYzRYuNXDwdujzvX9rB5 bF5S79G3ZRWjx/Zr85g9Pm+SC2CNamC0yUhNTEktUkjNS85PycxLt1XyDo53jjc1MzDUNbS0 MFdSyEvMTbVVcvEJ0HXLzAE6TEmhLDGnFCgUkFhcrKRvh2lCaIibrgVMY4Sub0gQXI+RARpI WMOY0bDgMkvBL7eKST17mRsYd9p0MXJySAiYSByfvoIdwhaTuHBvPVsXIxeHkMB0Romv59Yz QTgTmCR2rvoBVsUmoCNx481vRhBbRMBJ4tuRa2BFzAJ3GSWOPfwGlhAWiJK4vP4KM4jNIqAq 8XTNHTCbV8BV4ur8z0A2B9A6BYk5k8Cu4BRwk2h+fQNsvhBQyY8TV1gmMPIuYGRYxSiaWpBc UJyUnmukV5yYW1yal66XnJ+7iREcac+kdzCuarA4xCjAwajEw7th7rVgIdbEsuLK3EOMEhzM SiK869WuBwvxpiRWVqUW5ccXleakFh9iNAU6aiKzlGhyPjAJ5JXEGxqbmJsam1qaWJiYWSqJ 8x5stQ4UEkhPLEnNTk0tSC2C6WPi4JRqYDRlfsw5LWBmsndXE9Pe5HfLLyjKpRuaFU68HabF EFeiXryZL69bSfLqkeezmz2mG/Uzq64wNK0yeP/TeHX+57+cx7pyQvTltGZvd74Z/7jkT1SD TrlI8PE5CdOcGWyOJ04Q3hKu9e3lx2tBy0uTBM2mbOwrXySQsfF5i6f0o61aVZuaE2M/KLEU ZyQaajEXFScCAEf7MqjKAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: thomas.ab@samsung.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.178 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , With some of the Exynos SoCs switched over to use the generic CPUfreq drivers, the unused clock aliases can be removed. In addition to this, the individual clock blocks which are now encapsulated with the consolidate CPU clock type can now be marked with read-only flags. Cc: Tomasz Figa Signed-off-by: Thomas Abraham --- drivers/clk/samsung/clk-exynos4.c | 44 +++++++++++++++++++--------------- drivers/clk/samsung/clk-exynos5250.c | 19 ++++++++------- drivers/clk/samsung/clk-exynos5420.c | 27 ++++++++++++++------- 3 files changed, 54 insertions(+), 36 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 5388806..b482e39 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -578,7 +578,8 @@ static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4), MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4), MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1), - MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1), + MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1, 0, + CLK_MUX_READ_ONLY), MUX(0, "mout_hpm", mout_core_p4210, SRC_CPU, 20, 1), MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1), MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), @@ -714,15 +715,24 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = { DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus", CLKOUT_CMU_RIGHTBUS, 8, 6), - DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3), - DIV(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3), - DIV(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3), - DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3), - DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3), - DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3), - DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3), - DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3), - DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3), + DIV_F(0, "div_core", "mout_core", DIV_CPU0, 0, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_periph", "div_core2", DIV_CPU0, 12, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_atb", "mout_core", DIV_CPU0, 16, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_core2", "div_core", DIV_CPU0, 28, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6), DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4), @@ -770,8 +780,10 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = { DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8), DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4), DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4), - DIV(CLK_ARM_CLK, "arm_clk", "div_core2", DIV_CPU0, 28, 3), - DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), + DIV_F(CLK_ARM_CLK, "arm_clk", "div_core2", DIV_CPU0, 28, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4, CLK_SET_RATE_PARENT, 0), DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8, @@ -1194,10 +1206,6 @@ static struct samsung_clock_alias exynos4_aliases[] __initdata = { ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"), }; -static struct samsung_clock_alias exynos4210_aliases[] __initdata = { - ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"), -}; - static struct samsung_clock_alias exynos4x12_aliases[] __initdata = { ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"), }; @@ -1465,8 +1473,6 @@ static void __init exynos4_clk_init(struct device_node *np, ARRAY_SIZE(exynos4210_div_clks)); samsung_clk_register_gate(ctx, exynos4210_gate_clks, ARRAY_SIZE(exynos4210_gate_clks)); - samsung_clk_register_alias(ctx, exynos4210_aliases, - ARRAY_SIZE(exynos4210_aliases)); samsung_clk_register_fixed_factor(ctx, exynos4210_fixed_factor_clks, ARRAY_SIZE(exynos4210_fixed_factor_clks)); @@ -1501,7 +1507,7 @@ static void __init exynos4_clk_init(struct device_node *np, exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12", _get_rate("sclk_apll"), _get_rate("sclk_mpll"), _get_rate("sclk_epll"), _get_rate("sclk_vpll"), - _get_rate("arm_clk")); + _get_rate("armclk")); } diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index e19e365..1d958f1 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -291,14 +291,14 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { /* * CMU_CPU */ - MUX_FA(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, - CLK_SET_RATE_PARENT, 0, "mout_apll"), - MUX_A(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"), + MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, + CLK_SET_RATE_PARENT, 0), + MUX_F(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, 0, CLK_MUX_READ_ONLY), /* * CMU_CORE */ - MUX_A(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"), + MUX(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1), /* * CMU_TOP @@ -380,9 +380,12 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = { /* * CMU_CPU */ - DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), - DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3), - DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"), + DIV_F(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), /* * CMU_TOP @@ -848,6 +851,6 @@ static void __init exynos5250_clk_init(struct device_node *np) samsung_clk_of_add_provider(np, ctx); pr_info("Exynos5250: clock setup completed, armclk=%ld\n", - _get_rate("div_arm2")); + _get_rate("armclk")); } CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init); diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index d7ef36a..fcf365d 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -617,10 +617,14 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2), MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2), - MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1), - MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), - MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1), - MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), + MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, + CLK_SET_RATE_PARENT, 0), + MUX_F(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, 0, + CLK_MUX_READ_ONLY), + MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1, + CLK_SET_RATE_PARENT, 0), + MUX_F(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1, 0, + CLK_MUX_READ_ONLY), MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2), MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2), @@ -776,11 +780,16 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { }; static struct samsung_div_clock exynos5x_div_clks[] __initdata = { - DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), - DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), - DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), - DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3), - DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), + DIV_F(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "armclk2", "div_arm", DIV_CPU0, 28, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3), DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),