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[209.132.180.67]) by mx.google.com with ESMTP id la14si13185408pab.163.2014.06.16.03.28.11; Mon, 16 Jun 2014 03:28:11 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932161AbaFPK2I (ORCPT + 9 others); Mon, 16 Jun 2014 06:28:08 -0400 Received: from mail-pa0-f48.google.com ([209.85.220.48]:36618 "EHLO mail-pa0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755351AbaFPK0s (ORCPT ); Mon, 16 Jun 2014 06:26:48 -0400 Received: by mail-pa0-f48.google.com with SMTP id et14so3073918pad.35 for ; Mon, 16 Jun 2014 03:26:47 -0700 (PDT) X-Received: by 10.68.229.68 with SMTP id so4mr22740919pbc.110.1402914407691; Mon, 16 Jun 2014 03:26:47 -0700 (PDT) Received: from localhost.localdomain ([14.140.216.146]) by mx.google.com with ESMTPSA id gr10sm17922046pbc.84.2014.06.16.03.26.43 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 16 Jun 2014 03:26:47 -0700 (PDT) From: Chander Kashyap To: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, daniel.lezcano@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, kgene.kim@samsung.com, tomasz.figa@gmail.com, Chander Kashyap , Chander Kashyap Subject: [Patch v7 2/6] arm: exynos: add generic function to calculate cpu number Date: Mon, 16 Jun 2014 15:56:19 +0530 Message-Id: <1402914383-20471-3-git-send-email-k.chander@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1402914383-20471-1-git-send-email-k.chander@samsung.com> References: <1402914383-20471-1-git-send-email-k.chander@samsung.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Original-Sender: linux-kernel-owner@vger.kernel.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2607:f8b0:400c:c03::236 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=neutral (body hash did not verify) header.i=@ Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Chander Kashyap The address of cpu power registers in pmu is based on cpu number offsets. This function calculate the same. This is essentially required in case of multi-cluster SoC's e.g Exynos5420. Signed-off-by: Chander Kashyap Signed-off-by: Chander Kashyap Reviewed-by: Tomasz Figa --- arch/arm/mach-exynos/regs-pmu.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h index 1d13b08..aff23bd 100644 --- a/arch/arm/mach-exynos/regs-pmu.h +++ b/arch/arm/mach-exynos/regs-pmu.h @@ -323,4 +323,13 @@ #define EXYNOS5420_SWRESET_KFC_SEL 0x3 +#include +#define MAX_CPUS_IN_CLUSTER 4 + +static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr) +{ + return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER) + + MPIDR_AFFINITY_LEVEL(mpidr, 0)); +} + #endif /* __ASM_ARCH_REGS_PMU_H */