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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D5.mail.protection.outlook.com (10.167.241.76) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7249.19 via Frontend Transport; Fri, 2 Feb 2024 08:56:13 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Fri, 2 Feb 2024 02:56:10 -0600 From: Perry Yuan <perry.yuan@amd.com> To: <rafael.j.wysocki@intel.com>, <Mario.Limonciello@amd.com>, <viresh.kumar@linaro.org>, <Ray.Huang@amd.com>, <gautham.shenoy@amd.com>, <Borislav.Petkov@amd.com> CC: <Alexander.Deucher@amd.com>, <Xinmei.Huang@amd.com>, <Xiaojian.Du@amd.com>, <Li.Meng@amd.com>, <linux-pm@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH v2 0/6] AMD Pstate Fixes And Enhancements Date: Fri, 2 Feb 2024 16:55:32 +0800 Message-ID: <cover.1706863981.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: <linux-pm.vger.kernel.org> List-Subscribe: <mailto:linux-pm+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-pm+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D5:EE_|LV8PR12MB9271:EE_ X-MS-Office365-Filtering-Correlation-Id: 677fe42a-0b35-49ca-0ffb-08dc23cccf79 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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| Series |
AMD Pstate Fixes And Enhancements
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The patch series adds some fixes and enhancements to the AMD pstate driver. It enables CPPC v2 for certain processors in the family 17H, as requested by TR40 processor users who expect improved performance and lower system temperature. Additionally, it fixes the initialization of nominal_freq for each cpudata and changes latency and delay values to be read from platform firmware firstly for more accurate timing. A new quirk is also added for legacy processors that lack CPPC capabilities which caused the pstate driver to fail loading. I would greatly appreciate any feedbacks. Thank you! Changes from v1: * pick up the RB flags from Mario * address review comment of patch #6 for amd_get_nominal_freq() * rebased the series to linux-pm/bleeding-edge v6.8.0-rc2 * update debug log for patch #5 as Mario suggested. * fix some typos and format problems * tested on 7950X platform V1: https://lore.kernel.org/lkml/63c2b3d7-083a-4daa-ba40-629b3223a92d@mailbox.org/ Perry Yuan (6): ACPI: CPPC: enable AMD CPPC V2 support for family 17h processors cpufreq:amd-pstate: fix the nominal freq value set cpufreq:amd-pstate: initialize nominal_freq of each cpudata cpufreq:amd-pstate: get pstate transition delay and latency value from ACPI tables cppc_acpi: print error message if CPPC is unsupported cpufreq:amd-pstate: add quirk for the pstate CPPC capabilities missing arch/x86/kernel/acpi/cppc.c | 2 +- drivers/acpi/cppc_acpi.c | 4 +- drivers/cpufreq/amd-pstate.c | 108 +++++++++++++++++++++++++++++------ include/linux/amd-pstate.h | 6 ++ 4 files changed, 101 insertions(+), 19 deletions(-)