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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230016)(4636009)(346002)(39860400002)(376002)(136003)(396003)(46966006)(36840700001)(40470700004)(16526019)(86362001)(186003)(7696005)(356005)(70586007)(6666004)(2906002)(336012)(8676002)(478600001)(4326008)(2616005)(426003)(70206006)(26005)(54906003)(110136005)(41300700001)(966005)(47076005)(316002)(82310400005)(40460700003)(81166007)(36860700001)(36756003)(40480700001)(5660300002)(83380400001)(8936002)(82740400003)(6636002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2022 10:03:53.6328 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b449f3db-cd79-478d-69dc-08da664952fc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4018 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org This patchsets adds support for precision boost hardware control for AMD processors. Meanwhile the patchset fixs lowest perf query and desired perf scope issues. Update transition delay and latency default value to meet SMU firmware requirement. and do some code cleanups, It also exports cpufreq cpu release and acquire for coming amd-pstate epp mode driver The patch series are tested on the AMD mobile and EYPC server systems v3->v4: - check cached bit for core performance boost from hardware configuration register - pick up the Acked-by flags from Viresh and Sudeep v2->v3: - drop cpufreq cpu release and acquire export patch - remove the clamp_t in the amd_pstate_adjust_perf() v1->v2: - add two new patches to remove the acpi_disabled check - fix some typos in the commit info - move the clamp_t() into amd_pstate_update() function - rebased to 5.19-rc5 [v3] https://lore.kernel.org/all/20220713052944.xpk4fi7nuj6rmekd@vireshk-i7/t/ [v2]:https://lore.kernel.org/lkml/20220709140835.830084-1-Perry.Yuan@amd.com/ [v1]:https://patchwork.kernel.org/project/linux-pm/list/?series=657510 Perry Yuan (13): x86/msr: Add the MSR definition for AMD CPPC hardware control. cpufreq: amd-pstate: enable AMD Precision Boost mode switch cpufreq: amd-pstate: cleanup the unused and duplicated headers declaration cpufreq: amd-pstate: prefetch cppc_req_cached value in amd_pstate_cpu_init() cpufreq: amd-pstate: simplify cpudata pointer assignment cpufreq: amd_pstate: fix wrong lowest perf fetch cpufreq: amd_pstate: map desired perf into pstate scope for powersave governor cpufreq: amd-pstate: fix white-space cpufreq: amd-pstate: update pstate frequency transition delay time cpufreq: amd-pstate: add ACPI disabled check in acpi_cpc_valid() cpufreq: amd_pstate: update transition delay time to 1ms arch_topology: remove the acpi_disabled check cpufreq: CPPC: remove the acpi_disabled check arch/x86/include/asm/msr-index.h | 3 ++ drivers/acpi/cppc_acpi.c | 3 ++ drivers/base/arch_topology.c | 2 +- drivers/cpufreq/amd-pstate.c | 62 +++++++++++++++++++------------- drivers/cpufreq/cppc_cpufreq.c | 2 +- 5 files changed, 45 insertions(+), 27 deletions(-)