From patchwork Fri Aug 2 18:15:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rafael J. 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Wysocki" To: x86 Maintainers Cc: LKML , Linux PM , Thomas Gleixner , Peter Zijlstra , Srinivas Pandruvada , "Rafael J. Wysocki" , Dietmar Eggemann , Ricardo Neri , Tim Chen Subject: [PATCH v1 0/3] x86 / intel_pstate: Set asymmetric CPU capacity on hybrid systems Date: Fri, 02 Aug 2024 20:15:10 +0200 Message-ID: <4908113.GXAFRqVoOG@rjwysocki.net> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CLIENT-IP: 195.136.19.94 X-CLIENT-HOSTNAME: 195.136.19.94 X-VADE-SPAMSTATE: spam:low X-VADE-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeeftddrkedtgdduvdefucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecujffqoffgrffnpdggtffipffknecuuegrihhlohhuthemucduhedtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenogfuphgrmhfkphculdeftddtmdenucfjughrpefhvfevufffkfgggfgtsehtufertddttdejnecuhfhrohhmpedftfgrfhgrvghlucflrdcuhgihshhotghkihdfuceorhhjfiesrhhjfiihshhotghkihdrnhgvtheqnecuggftrfgrthhtvghrnhepgeffhfdujeelhfdtgeffkeetudfhtefhhfeiteethfekvefgvdfgfeeikeeigfehnecuffhomhgrihhnpehkvghrnhgvlhdrohhrghenucfkphepudelhedrudefiedrudelrdelgeenucfuphgrmhfkphepudelhedrudefiedrudelrdelgeenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepihhnvghtpeduleehrddufeeirdduledrleegpdhhvghlohepkhhrvggrtghhvghrrdhlohgtrghlnhgvthdpmhgrihhlfhhrohhmpedftfgrfhgrvghlucflrdcuhgihshhotghkihdfuceorhhjfiesrhhjfiihshhotghkihdrnhgvtheqpdhnsggprhgtphhtthhopedutddprhgtphhtthhopeigkeeisehkvghrnhgvlhdrohhrghdprhgtphhtthhopehlihhnuhigqdhkvghrnhgvlhesvhhgvghrrdhkvghrnhgvlhdrohhrghdprhgtphhtthhopehlihhnuhigqdhpmhesvhhgvghrrdhkvghrnhgvlhdrohhrghdprhgtphhtthhopehtghhlgieslhhinhhuthhrohhnihigrdguvgdprhgtphhtthhopehpvghtvghriiesihhnfhhrrgguvggrugdrohhrghdprhgtphhtthhopehsrhhinhhivhgrshdrphgrnhgurhhuvhgruggrsehlihhnuhigrdhinhhtvghlrdgtohhmpdhrtghpthhtoheprhgrfhgrvghlsehkvghrnhgvlhdrohhrghdprhgtphhtthhopeguihgvthhmrghrrdgvghhgvghmrghnnhesrghrmhdrtghomh X-DCC--Metrics: v370.home.net.pl 1024; Body=30 Fuz1=30 Fuz2=30 Hi Everyone, The purpose of this series is to provide the scheduler with asymmetric CPU capacity information on x86 hybrid systems based on Intel hardware. The asymmetric CPU capacity information is important on hybrid systems as it allows utilization to be computed for tasks in a consistent way across all CPUs in the system, regardless of their capacity. This, in turn, allows the schedutil cpufreq governor to set CPU performance levels consistently in the cases when tasks migrate between CPUs of different capacities. It should also help to improve task placement and load balancing decisions on hybrid systems and it is key for anything along the lines of EAS. The information in question comes from the MSR_HWP_CAPABILITIES register and is provided to the scheduler by the intel_pstate driver, as per the changelog of patch [3/3]. Patch [2/3] introduces the arch infrastructure needed for that (in the form of a per-CPU capacity variable) and patch [1/3] is a preliminary code adjustment. This is based on an RFC posted previously https://lore.kernel.org/linux-pm/7663799.EvYhyI6sBW@kreacher/ but differs from it quite a bit (except for the first patch). The most significant difference is based on the observation that frequency- invariance needs to adjusted to the capacity scaling on hybrid systems for the complete scale-invariance to work as expected. Thank you!